3 Assembly Programming (Part 2) Date: 07/09/2016 Name: ID:

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1 3 Assembly Programming (Part 2) 43 Date: 07/09/2016 Name: ID: Name: ID: 3 Assembly Programming (Part 2) This laboratory session discusses about Secure Shell Setup and Assembly Programming. The students should be able to do the followings: Output to the terminal Get input from key board Loop programming Barrel shifter 3.1 ARM Registers ARM processors provide general-purpose and sepcial-purpose registers. Some additional registers are available in privileged execution mode. In all ARM processors, the following registers are available and accessible in any processor mode: 13 general-purpose registers R0-R12 One Stack Pointer (SP) One Link Register (LR) One Program Counter (PC) One Appplication Program Register (APSR) General Purpose Register There are restrictions on the use of SP and LR as general-purpose registers.

2 3 Assembly Programming (Part 2) 44 With the exception of ARMv6-M and ARMv7-M based processors, there are 30 (or 32 if Security Extensions are implemented) general-purpose 32-bit registers, that include the banked SP and LR registers. Fifteen general-purpose registers are visible at any one time, depending on the current processor mode. These are R0-R12, SP, LR. The PC (R15) is not considered a general-purpose register. SP (or R13) is the stack pointer. The C and C++ compilers always use SP as the stack pointer. Use of SP as a general purpose register is discouraged. In Thumb, SP is strictly defined as the stack pointer. The instruction descriptions mention when SP and PC can be used. In User mode, LR (or R14) is used as a link register to store the return address when a subroutine call is made. It can also be used as a general-purpose register if the return address is stored on the stack. In the exception handling modes, LR holds the return address for the exception, or a subroutine return address if subroutine calls are executed within an exception. LR can be used as a general-purpose register if the return address is stored on the stack Register Accesses 16-bit Thumb instructions can access only a limited set of registers. There are also some restrictions on the use of special-purpose registers by ARM and 32-bit Thumb instructions. Most 16-bit Thumb instructions can only access R0 to R7. Only a small number of these instructions can access R8-R12, SP, LR, and PC. Registers R0 to R7 are called Lo registers. Registers R8-R12, SP, LR, and PC are called Hi registers. All 32-bit Thumb instructions can access R0 to R12, and LR. However, apart from a few designated stack manipulation instructions, most Thumb instructions cannot use SP. Except for a few specific instructions where PC is useful, most Thumb instructions cannot use PC. In ARM state, all instructions can access R0 to R12, SP, and LR, and most instructions can also access PC (R15). However, the use of the SP in an ARM instruction, in any way that is not possible in the corresponding Thumb instruction, is deprecated. Explicit use of the PC in an ARM instruction is not usually useful, and except for specific instances that are useful, such use is deprecated. Implicit use of the PC, for example in branch instructions or load (literal) instructions, is never deprecated.

3 3 Assembly Programming (Part 2) Hello World 1. Create a new directory under the pi user, i.e. /home/pi/assemblylabs/lab3 2. Naavigate to such directory such that when you type in pwd command you should be on the directory /home/pi/assemblylabs/lab3 3. Create a new assembly file vim Lab3.s using vim 4. Create a makefile to run the program Lab3.s 5. Enter the following code:.global _start _start: MOV R7, #4 MOV R0, #1 MOV R2, #12 LDR R1, Write to the Output to the Length of output string end: MOV R7, Jump to the terminal.data message:.ascii Hello World\n 6. Run the makefile 7. Type.\Lab3 and record the result

4 3 Assembly Programming (Part 2) Keyboard Input 1. Modify the code of Lab3.s as follows:.global _start _start: MOV R7, #3 MOV R0, #0 MOV R2, #10 LDR R1, System call Input from Length of input string _write: MOV R7, #4 MOV R0, #1 MOV R2, #5 LDR R1, =message end: MOV R7, Jump to the terminal.data message:.ascii 2. Run the makefile 3. Type.\Lab3 input the string and record the result

5 3 Assembly Programming (Part 2) Assignment The instruction BIC has the following syntax: BIC Rd, Rn, Operand2 The BIC(Bit Clear) instruction performs an AND operation on the bits in Rn with the complements of the corresponding bits in the value of operand2 Write an assembly program that receive a lower case character from keyboard as an input, e.g. a, and output the corresponding uppercase letter to the screen, e.g. A. Hint: Use LDR and STR to load and store the value/address to the register. Use ASCII code table to see the binary code of the character. Use BIC command in uppercase transformation

6 3 Assembly Programming (Part 2) Looping Performin looping in the program is one of the important ingredient in programming. In this case, the program will perform the task until the pre-set conditions are met First Looping In general, performing looping, for example a while loop, has the following structure R0 = 0 while(r0 <= 10) R0 = R0+1 This can also be done in assembly language. The following program illustrates it. 1. Modify the code of Lab3.s as follows:.global _start _start: MOV R0, #0 MOV R1, #1 B _continue_loop _loop: ADD R0, R0, R1 _continue_loop: CMP R0, #9 BLE _loop end: MOV R7, #1 2. Run the makefile

7 3 Assembly Programming (Part 2) Type.\Lab3 ; echo $? and record the result 4. Explain the program and the result Current Program Status Register The Current Program Status Register is a 32-bit wide register used in the ARM architecture to record various pieces of information regarding the state of the program being executed by the processor and the state of the processor. This information is recorded by setting or clearing specific bits in the register. This is shown in Figure 3.1 Condition code flags The N, Z, C, and V bits are the condition code flags. They can be by arithmetic and logical operations. They can also be set by MSR and LDM instructions. The ARM processor tests these flags to determine whether to execute an instruction.

8 3 Assembly Programming (Part 2) 50 Figure 3.1: Current Program Status Register All instructions can execute conditionally in ARM state. In Thumb state, only the Branch instruction can be executed conditionally. Control bits The bottom eight bits of a PSR are known collectively as the control bits. They are the: Interrupt disable bits T bit mode bits The control bits change when an exception occurs. When the processor is operating in a privileged mode, software can manipulate these bits. Reserved bits The remaining bits in the CPSRs are unused, but are reserved. When changing a PSR flag or control bits, make sure that these reserved bits are not altered. Also, make sure that your program does not rely on reserved bits containing specific values because future processors might have these bits set to 1 or Conditional Programming The following list show the conditional code which can be used in the program in order to make the program operates according to the desired conditions.

9 3 Assembly Programming (Part 2) 51 EQ : Z Set NE : Z Not Set CS : Carry Set CC : Carry Not Set MI : Negative Set PL : Negative Not Set VS : Overflow Set VC : Overflow Not Set HI : Carry &!Zero LS : Carry & Zero GE : Negative == Overflow LT : Negative!= Overflow GT :!Zero && Negative = Overflow LE : Zero Negative!= Overflow Second Looping Now, we would like to perform the loop as shown in the following: R0 = 50 R1 = 2 while(r0 > R1) R0 -= 2 1. Modify the code of Lab3.s as follows:.global _start _start: MOV R0, #50 MOV R1, #2 B _loop _decrement: SUBGT R0, R0, R1 _loop: CMP R0, R1 BNE _decrement

10 3 Assembly Programming (Part 2) 52 end: MOV R7, #1 2. Run the makefile 3. Type.\Lab3 ; echo $? and record the result 4. Explain the program and the result Assignment Write assembly program which add the even number from 0 to 9 and output to the screen.

11 3 Assembly Programming (Part 2) Barrel Shifter The barrel shifter is a functional unit which can be used in a number of different circumstances. It provides five types of shifts and rotates which can be applied to Operand2. (These are not operations themselves in ARM mode.) Logical Shift Left (LSL) Example of Logical Shift Left by 4 is shown in Figure 3.2. This is equivalent to << in C. Figure 3.2: LogicalShiftLeft Logical Shift Right (LSR) Example of Logical Shift Right by 4 is shown in Figure 3.3. This is equivalent to >> in C, i.e. unsigned division by a power of 2. Figure 3.3: LogicalShiftRight Arithmetic Shift Right (ASR) Example of Arithmetic Shift Right by 4, positive valueis is shown in Figure 3.4 Figure 3.4: ArithmeticShiftRight(positivevalue) Example of Arithmetic Shift Right by 4, negative value is shown in Figure 3.5 This is equivalent to >> in C, i.e. signed division by a power of 2. Rotate Right (ROR) Example of Rotate Right by 4 is shown in Figure 3.6. This is a bit rotation with wrap-around.

12 3 Assembly Programming (Part 2) 54 Figure 3.5: ArithmeticShiftRight(negativevalue) Figure 3.6: RotateRight Rotate Right Extended (RRX) Example of Rotate Right Extended is shown in Figure 3.7. This is a 33-bit rotation with wrap-around through carry bit. Figure 3.7: Rotate Right Extended 1. Modify the code of Lab3.s as follows:.global _start _start: MOV R1, #15 MOV R0, R1, LSL #1 end: MOV R7, #1 2. Run the makefile

13 3 Assembly Programming (Part 2) Type.\Lab3 ; echo $? and record the result 4. Explain the program and result Assignment Write an assembly program which accepts a number n (0-9) from keyboard. The program then calculates 4 n and output to the screen using barrel shifter command. Write an assembly program whcih sets R3=5 and then divide R3 by 2. Output the result to the screen. Explain the result.