Instruction Set II. COMP 212 Computer Organization & Architecture. COMP 212 Fall Lecture 7. Instruction Set. Quiz. What is an Instruction Set?

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1 COMP 212 Computer Organization & Architecture Quiz COMP 212 Fall 2008 Lecture 7 Fill in your student number only, do NOT write down your name Open book, but NO calculator, NO discussions, Relax and have fun Instruction Set II Comp 212 Computer Org & Arch 1 Z. Li, 2008 Comp 212 Computer Org & Arch 2 Z. Li, 2008 Instruction Set What is an Instruction Set? Complete collections of all instructions that can be understood by Instruction Set Overview certain family of CPU» E.g. X86 instruction set, MIPS instruction set, ARM instruction set, PowerPC instruction set It is in binary form called Machine Code For programmer, we have Assembly Code representation. Comp 212 Computer Org & Arch 3 Z. Li, 2008 Comp 212 Computer Org & Arch 4 Z. Li, 2008

2 Instruction Elements Machine code format Recap of Instruction Cycles CPU can not directly operates on memory Data/Instructions have to be loaded into Registers Elements of an Instruction Operation Code:» Do what? ADD, LOAD, MOVE..etc. Source Operand reference:» On what? Register/Mem location, etc. Result/Target Operand Reference:» To where? Registers/mem locations etc. Next Instruction Reference» What is the next PC? Comp 212 Computer Org & Arch 5 Z. Li, 2008 Instruction word has unique bit patterns, e.g. 16 bit instruction can be partitioned into: 4-bit Opcode: what to do 6-bit Operand ref 1: 6-bit Operand ref 2: E.g.: ADD R1, R2 = Assembly Code Give it a human readable form Comp 212 Computer Org & Arch 6 Z. Li, 2008 Where are the operands? Operands can be in: Registers inside CPU:» eg. ADD R1, R2, add values in R1 and R2, store in R1 Main memory» eg. LOAD R1, [R2]: load memory location stored in R2 into R1. IO Device (memory mapped) Addressing mode: how to specify the location? Immediate (within the instruction) Register Memory Location indicated by a register Will cover in more detail in the next lecture. Number of Addresses in Instruction 4-addresses 2 source operands addr, 1 destination operand addr, and 1 next instruction addr,» e.g. ADD R1, R2, R3, R4 ; %% R1=R2+R3; PC=R4. But rarely implemented. 3-addresses 2 source operands, 1 destination operands» E.g. ADD R1, R2, R3 ; %% R1=R2+R3; PC=PC+1 No good, requires long instruction word to implement. Comp 212 Computer Org & Arch 7 Z. Li, 2008 Comp 212 Computer Org & Arch 8 Z. Li, 2008

3 Number of Addresses in Instruction 2-addresses 1 source and destination operand, 1 source:» e.g. ADD R1, R2; %% R1=R1+R2; PC=PC+1;» E.g. MOVE R2, R3; %%% R2 = R3; Common in modern instruction set implementations. 1-addresses Have an implicit operands, e.g. AC register» E.g. ADD R1 ; %% AC=AC+R1; PC=PC+1 Also quite common 0-address. Stack operation (in more details later), all addresses implicit. How many addresses is good? More addresses: More complex (powerful also?) instructions Fewer instructions per program Can specify more registers Longer instruction takes longer to fetch/execute. Fewer addresses: Less complex instructions More instructions per program But faster instruction fetch and execution. Comp 212 Computer Org & Arch 9 Z. Li, 2008 Comp 212 Computer Org & Arch 10 Z. Li, 2008 Example 3 vs 2 vs 1 Operands How many addresses is good? Instruction Format Length in bits, 16, 32, or 64 bits? Registers: Instruction Set Design Number of registers can be referenced by the instructions and their usage, e.g. AC, PC vs general purpose registers, Rx. Addressing: Modes of reference operand (in more detail later) Data types: What to support and how they operate, e.g. int, int32, float, double. Operation repertoire: How many operations to provide, how they relate to each other. Limited to 2 n operations for n-bit opcode. Comp 212 Computer Org & Arch 11 Z. Li, 2008 Comp 212 Computer Org & Arch 12 Z. Li, 2008

4 Operand (Data) Types ASCII (informational) Addresses How to interpret addresses? Numbers: Integer, Floating point, Decimal (BCD):» need 4-bit per decimal number, i.e., 0000 = 0, 0001=1,, 1000=9, 1001=9. Characters: To store text strings, e.g., ASCII code, 7-bit defines 128 characters. Logical Data: For a given n-bit data, considered to be n elements Support bit wise operations.. Comp 212 Computer Org & Arch 13 Z. Li, 2008 Comp 212 Computer Org & Arch 14 Z. Li, 2008 Instruction Types Typically, instructions can be grouped into the following types: Data transfer and IO Arithmetic (1) Data Transfer Instructions Need to specify» Source, Destination» Amount of data to be transferred Pentium Data Transfer Instructions: Logical Conversion System Control The instruction set on MIPS will be covered in more detail for a mini project Comp 212 Computer Org & Arch 15 Z. Li, 2008 Comp 212 Computer Org & Arch 16 Z. Li, 2008

5 (2) Arithmetic (3) Logical Numerical computing: Addition, subtraction, division, multiplication Pentium Arithmetic Instructions: Bit-wise operations on operand Pentium Logical Instructions: AND bit wise and operation SHL/SHR: bit wise shift Comp 212 Computer Org & Arch 17 Z. Li, 2008 Comp 212 Computer Org & Arch 18 Z. Li, 2008 Basic Logical Operations: (3) Logical Basic Logical Operations: (4) System Controls AND, OR and XOR on P and Q: JMP: set PC to the value specified in JMP JE/Z: JMP if certain register specified equal to zero. Shift operations: CALL: save all program execution context, i.e. all registers, and jump to a segment of program. When complete, load context and continue the execution. Branch operation:» IF R1=0 JMP to 1000h, ELSE JMP to 1200h. See HW.1Q.4 Comp 212 Computer Org & Arch 19 Z. Li, 2008 Comp 212 Computer Org & Arch 20 Z. Li, 2008

6 Stack and Function Calls Stack is a data structure implemented in hardware that Supports FILO operations, Lec07-Stack» ie. Data are PUSHed into stack in order of say, 1, 2, 3, 4, but when POP, goes up by the order of 4, 3, 2, 1.» What is the pop result if we have:» PUSH 1O» PUSH 15» PUSH 16» POP» Stack would have 10<15<16, when pop, the TOP of the stack is 16, so 16 is out. Comp 212 Computer Org & Arch 21 Z. Li, 2008 Comp 212 Computer Org & Arch 22 Z. Li, 2008 Stack and Function Calls What is the use of Stack? One important application is Procedural control A procedure is a collection of instruction sequence that do certain job..e.g compute X+Y and store in Z. It can be CALLed multiple times Stack is used to remember the right PC address for programs to return to the right sequence. Stack and Function Calls CALL Push the next PC into stack, RETRUN Pop the Stack value to PC. Comp 212 Computer Org & Arch 23 Z. Li, 2008 Comp 212 Computer Org & Arch 24 Z. Li, 2008

7 Stack and Function Calls For the sequence of execution above: 4000: CALL Proc 1 (at 4500) : PUSH 4101 to Stack JMP to : CALL Proc 2 (at 4800) : PUSH 4601 to Stack JMP to 4800 Proc 2 RETRUN: POP Stack: PC= 4601 At 4650 CALL Proc 2 (at4800): PUSH 4651 to Stack JMP to 4800 Proc 2 RETURN: POP: PC=4651 Proc 1 RETURNL PoP: PC=4101 Lec-07: Addressing Endian Issue Addressing Modes Comp 212 Computer Org & Arch 25 Z. Li, 2008 Comp 212 Computer Org & Arch 26 Z. Li, 2008 Little vs Big Endian Byte Order (example) What order do we read numbers that occupy more than one byte e.g. (numbers in hex to make it easy to read) can be stored in 4x8bit locations as follows How bytes are stored within a word (4 byte)? Consider 4 byte BCD word for , its storage in memory: Address Value (1) Value(2) Shall we read it in Big Endian (1) or Little Endian (2) way? Comp 212 Computer Org & Arch 27 Z. Li, 2008 Comp 212 Computer Org & Arch 28 Z. Li, 2008

8 Byte Order Names C Data Structure Word is 8 bytes The problem is called Endian: How to arrange bytes in a given word structure. The system on the left has the least significant byte in the lowest address, this is called big-endian The system on the right has the least significant byte in the highest address, this is called little-endian Comp 212 Computer Org & Arch 29 Z. Li, 2008 Comp 212 Computer Org & Arch 30 Z. Li, 2008 Standard for Endian Pentium (80x86), VAX are little-endian IBM 370, Moterola 680x0 (Mac), and most RISC are big-endian Internet is big-endian Makes writing Internet programs on PC more awkward! WinSock provides htoi and itoh (Host to Internet & Internet to Host) functions to convert Addressing Modes Immediate Address Direct (Memory) Address Indirect (Memory) Address Register (direct) Register Indirect Displacement (Indexed) Stack Comp 212 Computer Org & Arch 31 Z. Li, 2008 Comp 212 Computer Org & Arch 32 Z. Li, 2008

9 Immediate Addressing Opcode Operand Operand is part of instruction e.g. ADD 5: Add 5 to contents of accumulator, 5 is operand No memory reference to fetch data Fast But Limited range: E.g. 32 bit instruction, 4 bit opcode, only 28 bit operand Direct Addressing Diagram Address field contains address of operand Effective address (EA) = address field (A) e.g. ADD A Add contents of cell A to accumulator Look in memory at address A for operand Single memory reference to access data No additional calculations to work out effective address Still limited address space, usually less than word length in addressing space: Eg.. 32bit instruction, 4bit opcode, address space: 2 28 Comp 212 Computer Org & Arch 33 Z. Li, 2008 Comp 212 Computer Org & Arch 34 Z. Li, 2008 Indirect Addressing Memory cell pointed to by address field contains the address of (pointer to) the operand EA-Effective Address = (A) Look in A, find address (A) and look there for operand e.g. ADD (A) Add contents of cell pointed to by contents of A to accumulator Indirect Addressing Large address space, as the true address is stored in memory, can have potential 2 n where n = word length May be nested, multilevel, cascaded e.g. Effective Address EA = ((A)) A->A= :[ ]: : [ ] => EA= Multiple memory accesses to find operand Hence slower Comp 212 Computer Org & Arch 35 Z. Li, 2008 Comp 212 Computer Org & Arch 36 Z. Li, 2008

10 Register Addressing No memory access, very fast execution Direct Addressing: operand specify which register has the operand The operand is inside register Register Indirect Addressing Indirect Addressing via Registers Effective Address is stored inside register EA = (R) Operand is in memory cell pointed to by contents of register R Large address space (2 n ) One fewer memory access than indirect (mem) addressing Comp 212 Computer Org & Arch 37 Z. Li, 2008 Comp 212 Computer Org & Arch 38 Z. Li, 2008 Displacement Addressing Relative Addressing Address field hold two values: EA = A + (R), or ( R) +A A version of displacement addressing R = Program counter, PC A = base value R = register that holds displacement or vice versa Instruction Opcode Register R Address A Registers Memory EA = A + (PC) i.e. get operand from A cells from current location pointed to by PC c.f locality of reference & cache usage Pointer to Operand + Operand Comp 212 Computer Org & Arch 39 Z. Li, 2008 Comp 212 Computer Org & Arch 40 Z. Li, 2008

11 Base-Register Addressing Indexed Addressing A holds displacement R holds pointer to base address R may be explicit or implicit e.g. segment registers in 80x86 A = base R = displacement EA = A + R Good for accessing arrays EA = A + R R++ Comp 212 Computer Org & Arch 41 Z. Li, 2008 Comp 212 Computer Org & Arch 42 Z. Li, 2008 Combinations Stack Addressing Postindex R A Operand is (implicitly) on top of stack EA = (A) + (R) e.g. ADD Preindex EA = (A+(R)) EA = (A) + ( R )» Pop 2 operands and add them together (Draw the diagrams) Comp 212 Computer Org & Arch 43 Z. Li, 2008 Comp 212 Computer Org & Arch 44 Z. Li, 2008

12 Virtual or effective address is offset into Pentium Addressing Modes Lec 07 Instruction Set Examples (informational) segment Base address from segment register Effective or virtual address Linear hardware address = Base+Effective addresses Comp 212 Computer Org & Arch 45 Z. Li, 2008 Comp 212 Computer Org & Arch 46 Z. Li, 2008 LA = linear address Pentium Addressing Modes B = base register PowerPC Addressing Modes Load/store architecture Indirect» Instruction includes 16 bit displacement to be added to base register (may be GP register)» Can replace base register content with new address Indirect indexed» Instruction references base register and index register (both may be GP)» EA is sum of contents SR = seg register PC = program counter I = index register A = immediate addr in instruction R = register S = scaling factor Comp 212 Computer Org & Arch 47 Z. Li, 2008 Comp 212 Computer Org & Arch 48 Z. Li, 2008

13 PowerPC Addressing Modes Branch address Absolute» Unconditional jumps, addr from 24 bit immediate within the instruction» Conidtional jumps, 16 bit immediate addr» Effective Addr = extended 24/16 bit addr Relative» EA = (PC) + Immediate from instruction Indirect» From link/count registers ALU operations: Fixed point:» Operands in registers or part of instruction Floating point is register only Instruction Length issues What is a good instruction length? Affected by and affects: Opcode length:» more instructions if longer Addressing mode: Memory size / organization:» Longer instruction, larger addressing space» Wasteful, 64bit insturction vs 32 bit instruction, almost double the size of program. Bus structure:» want to have integer number of transfers to fetch an instruction CPU» Bottleneck if fetch is slower than execution, shorter instruction can be a solution. Trade off between powerful instruction repertoire and saving space Comp 212 Computer Org & Arch 49 Z. Li, 2008 Comp 212 Computer Org & Arch 50 Z. Li, 2008 Allocation of Bits Pentium Instruction Format Number of addressing modes Need some explicit signaling on this Number of operands Range and flexibility tradeoff: single operand, more instructions. Register versus memory 8~32 registers are desirable. Address range and granularity Number of bits used for address limits the range Comp 212 Computer Org & Arch 51 Z. Li, 2008 Comp 212 Computer Org & Arch 52 Z. Li, 2008

14 Pentium Instruction Variable lenth Opcode (1~2 bytes) Operations, also direction of operation to/from mem ModR/m (0~1 byte) Whether operand is in mem/reg. SIB (1 byte) Scale index base: scale (2 bits), index reg (3 bits) and base reg (3 bits), for addressing. Displacement (1~4 bytes) Number of bits used for address limits the range Immediate (1~4 bytes) Operand immediate. Summary Addressing Endian issue, an annoyance need to take care of Immediate, Direct, In-direct, Base+Offset, and combinations Stack FILO data structure Used in program control, e.g. system calls push/pop PCs. Instruction Set: Design issues: length, number of operands,,etc Types:» Data movement» Arithmetic and Logical» Program Control Comp 212 Computer Org & Arch 53 Z. Li, 2008 Comp 212 Computer Org & Arch 54 Z. Li, 2008