ENCM 501 Winter 2019 Assignment 6 for the Week of March 11

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1 page of 8 ENCM 5 Winter 29 Assignment 6 for the Week of March Steve Norman Department of Electrical & Computer Engineering University of Calgary February 29 Assignment instructions and other documents for ENCM 5 can be found at Administrative details Group work is permitted See the Assignment 3 instructions for for information about working in groups Due Dates The Due Date for this assignment is 3:3pm, Friday, March 5 The Late Due Date is 3:3pm, Monday, March 8 The penalty for handing in an assignment after the Due Date but before the Late Due Date is 3 marks In other words, X/Y becomes (X 3)/Y if the assignment is late There will be no credit for assignments turned in after the Late Due Date; they will be returned unmarked Marking scheme A B total 5 marks 2 marks 7 marks How to package and hand in your assignments Please see the instructions in Assignment And, if you are submitting a group assignment, please make sure that all group members names are clear and complete on the cover page Exercise A: x86-64 page tables Read This First As stated in the lecture Tuesday, February 26, 48-bit virtual addresses in x86-64 systems are used to search a four-level tree-like page table, with virtual page numbers split into four 9-bit chunks:

2 ENCM 5 Winter 29 Assignment 6 page 2 of 8 36-bit virtual page number VPN VPN 2 VPN 3 VPN 4 page offset Consider a tiny Linux-ish process that uses only three pages of virtual memory: VPN x4 x4 x7fffffffe Use instructions and read-only data readable/writeable static data stack These VPNs split as follows for page table access: VPN VPN VPN2 VPN3 VPN4 x4 2 x4 2 x7fffffffe Those VPN splits result in the page table structure shown in Figure It s not terribly space-efficient seven pages are needed for a page table supporting only three pages used by the process but it s much, much better than a simple array with indexes to x7ffffffff! What to Do Determine the memory footprint memory used for virtual pages plus memory used for a page table for a x86-64 Linux process with the fake but realistic use of virtual memory listed in Figure 2 To keep things relatively simple, count all of the pages related to shared libraries, despite the fact that that part of the footprint is probably shared with other processes Hints: Adding up the number of virtual pages is simple arithmetic You can use the program vpn-splitc to quickly split VPNs into 9-bit chunks To count directories, start by finding out how many page upper directories are needed For each page upper directory, find out how many page middle directories are needed Then for each page middle directory, find out how many last-level page tables are needed What to Hand In Hand in your calculations and results Describe your calculations with enough clarity and detail that a reader could understand exactly what your method was Remark The fake data for this exercise was generated by looking at the virtual memory layout of a real 64-bit Linux process, then simplifying it to make solving the exercise quite a bit less tedious See Figure 3 for more information, if you re curious I m not sure if it s possible to create a process this tiny on a real 64-bit Linux system

3 ENCM 5 Winter 29 Assignment 6 page 3 of 8 Figure : x86-64 page table organization for a process with only three pages The character represents a null pointer in the directories, and indicates no such page in the last-level page tables Each cell in a directory and each PTE is 64 bits wide, so the total memory footprint of the page table is 7 52 cells 8 bytes/cell = 7 4 KB page global directory page upper directories 5 5 page middle directories last-level page tables useful PTE useful PTE useful PTE Figure 2: Fake but fairly realistic information about how an x86-64 Linux process might use virtual memory VPN range x4 to x43 x6 to x62 x63 to x9d3 x34e8 to x34ef52 x7fff35c5 to x7fff35c7 Use instructions and read-only data readable/writeable static data heap shared-library instructions and data stack

4 ENCM 5 Winter 29 Assignment 6 page 4 of 8 Figure 3: Demonstration of finding the virtual memory layout of a Linux process I suspended a process, used ps to find its process ID, then used one of the facilities in the Linux /proc system This is real output, edited very slightly so that it wouldn t be too wide to fit legibly on letter-size paper --- remote:~/5/assign5 --> /aout sum of junk is ^Z []+ Stopped /aout --- remote:~/5/assign5 --> ps PID TTY TIME CMD 255 pts/ :: bash 2587 pts/ :: aout 2588 pts/ :: ps --- remote:~/5/assign5 --> cat /proc/2587/maps 4-4 r-xp :f /nfs/engfs/[]/aout 6-6 rw-p :f /nfs/engfs/[]/aout 6-4a2 rw-p : [heap] 34e8-34e8c r-xp 8: /lib64/ld-25so 34eac-34ead r--p c 8: /lib64/ld-25so 34ead-34eae rw-p d 8: /lib64/ld-25so 34ec-34ed4f r-xp 8: /lib64/libc-25so 34ed4f-34ef4e ---p 4f 8: /lib64/libc-25so 34ef4e-34ef52 r--p 4e 8: /lib64/libc-25so 34ef52-34ef53 rw-p 52 8: /lib64/libc-25so 34ef53-34ef58 rw-p : 34f8-34f86 r-xp 8: /lib64/libpthread-25so 34f86-34fa6 ---p 6 8: /lib64/libpthread-25so 34fa6-34fa7 r--p 6 8: /lib64/libpthread-25so 34fa7-34fa8 rw-p 7 8: /lib64/libpthread-25so 34fa8-34fac rw-p : r-xp 8: /lib64/librt-25so p 7 8: /lib64/librt-25so r--p 7 8: /lib64/librt-25so rw-p 8 8: /lib64/librt-25so 7f446666d-7f446666f rw-p : 7f446668a-7f446668d rw-p : 7fff94c3d-7fff94c5e rw-p : [stack] 7fff94da7-7fff94da8 r-xp : [vdso] ffffffffff6-ffffffffff6 r-xp : [vsyscall]

5 ENCM 5 Winter 29 Assignment 6 page 5 of 8 Exercise B: Tracing instructions through a 5-stage RISC-V pipeline Read This First To get a feel for how pipelining really works, nothing beats studying a pipelined circuit and tracing the flow of chunks of instructions and data through the circuit This exercise concerns study of how instructions are processed by a computer that aims to support a subset of RV32I, which is the 32-bit version of the core integer ISA of RISC-V In RV32I all instruction and data memory addresses are 32 bits wide, and GPRs are 32 bits wide as well The instructions in the subset are: five R-type instructions: ADD, SUB, SLT, OR, AND add immediate: ADDI load of a 32-bit word: LW store of a 32-bit word: SW branch if two GPRs are equal: BEQ The machine code formats of those instructions are shown in Figure 4 Figure 5 shows a schematic for a microarchitecture for the RV32I subset, with simple, idealized memory units and five pipeline stages The same figure shows a very similar microarchitecture for a subset of the MIPS ISA The microarchitecture for the MIPS subset has been an important subject of study in ENCM 369 every for the last several years Here are a few key points about the RV32 version of the circuit: Branch target address calculation in RISC-V is relative to the address of the branch instruction In MIPS, it s relative to the successor of the branch instruction That explains why the instruction address inputs to the registers between the F and D stages aren t exactly the same in the two schematics Generation of immediate mode operand values is very simple in the MIPS subset just sign-extend bits 5 of the instruction It s more complicated for the RISC-V subset, as you can see from the machine code formats in Figure 4 In the RV32 schematic, all the work of generating immediate mode operand values is lumped into the unit labeled immed gen In the RV32 schematic, comparison of GPRs in BEQ instructions is done with the unit labeled =? That makes the ALU available to do the addition that computes the branch target address Both the RV32 and the MIPS schematics are partly correct, but partly incorrect they don t manage RAW data hazards correctly, and they don t handle BEQ instructions correctly For BEQ the target addresses are computed correctly, but are written into the PC a few cycles too late What to Do Study the code fragment listed in Figure 6 You are going to trace execution of this code in the RV32I subset computer of Figure 5 starting with the lw instruction Assume the following initial values for registers and memory: x: x x3: x x: x4 x4: x4444 x2: x2222 memory at x: x2a

6 ENCM 5 Winter 29 Assignment 6 page 6 of 8 Figure 4: Machine code for the RV32I subset used in Exercise B These formats correspond exactly to RISC-V specifications rd specifies a destination GPR, if there is one rs specifies the first source GPR, and rs2 specifies the second source GPR, if there is one In R-type instructions the funct7 and funct3 fields both play roles in deciding what operation is to be performed by whatever elements compute the result The immediate value for ADDI and the offsets for LW, SW and BEQ are all signed integers represented in two s complement The complicated-looking format for the offset in BEQ supports the design of small, efficient circuits for generation of values to add to PC values in computation of branch target addresses R-type funct7 rs2 rs funct3 rd ADDI 3 2-bit immediate value rs rd LW 3 2-bit offset rs rd SW 3 offset[:5] rs rs offset[4:] BEQ offset[2,:5] rs2 rs offset[4:,] Assume also that ALUControlE = specifies addition and ALUControlE = specifies set-less-than Answer all of the following questions, giving brief explanations for your answers Use hexadecimal for 32-numbers and binary for 5-bit numbers and single bits When lw is in the F stage, what are the values of (a) PCF and (b) the output of I-Mem? 2 When lw is in the D stage and the first addi is in the F stage, what are the values of (a) PCF, (b) the output of I-Mem, (c) InstrD, and (d) the RD and RD2 outputs of the R-file? 3 When lw is in the E stage and the first addi is in the D stage, what are the values of (a) the control signals RegWriteE through ALUSrcE, (b) the A and B inputs to the ALU, (c) RdE, and (d) the RD and RD2 outputs of the R-file? 4 When lw is in the M stage and the first addi is in the E stage, what are the values of (a) the control signals RegWriteE through ALUSrcE, (b) the A and B inputs to the ALU, (c) RdE, (d) RdM and (e) the RD output of D-Mem? 5 When slt is in the E stage, what are the values of (a) the control signals Reg- WriteE through ALUSrcE, (b) the A and B inputs to the ALU, and (c) RdE? 6 When beq is in the E stage, what are the values of (a) the control signals RegWriteE through ALUSrcE, (b) the A and B inputs to the ALU, and (c) the inputs to the =? unit? 7 The circuit computes branch target addresses correctly, but, in the case of a taken branch, updates the PC a few cycles too late Exactly how many of the four addi instructions at the end of the code listing will be fetched before the lw instruction is fetched a second time?

7 ENCM 5 Winter 29 Assignment 6 page 7 of 8 Figure 5: Five-stage pipelines for an RV32I subset (top) and a MIPS32 subset (bottom) The MIPS32 schematic is Figure 747 from Harris D M and Harris S L, Digital Design and Computer Architecture, 2nd ed, c 23, Elsevier, Inc Both circuits are correct in many important ways but both fail to handle data hazards and control hazards correctly 3:25 4:2 6: Control RegWriteE MemtoRegE MemWriteE BranchE ALUControlE ALUSrcBE ALUSrcAE 3 RegWriteM MemtoRegM MemWriteM BranchM RegWriteW MemtoRegW PCF A RD I-Mem PCD InstrD =? 9:5 WE3 A RD WE A 24:2 ALUOutM A2 RD2 ALU A RD B A3 D-Mem WD3 R-File WD ALUOutW ReadDataW 4 + :7 3:2 : immed gen RdE ImmedE RdM RdW ResultW Control Unit 3:26 Op 5: Funct RegWriteD MemtoRegD MemWriteD BranchD ALUControlD ALUSrcD RegWriteE RegWriteM RegWriteW MemtoRegE MemtoRegM MemtoRegW MemWriteE BranchE ALUControlE 2: ALUSrcE MemWriteM BranchM PCSrcM PC' PCF A RD Instruction Memory InstrD 25:2 2:6 2:6 5: A A2 A3 WD3 RegDstD WE3 RD Register File RD2 RegDstE RtE RdE SrcAE SrcBE WriteDataE ALU WriteRegE 4: ZeroM WE ALUOutM A RD Data Memory WriteDataM WD WriteRegM 4: ALUOutW ReadDataW WriteRegW 4: PCPlus4F 4 + 5: PCPlus4D Sign Extend SignImmE PCPlus4E <<2 + PCBranchM ResultW

8 ENCM 5 Winter 29 Assignment 6 page 8 of 8 Figure 6: Listing of a code fragment for Exercise B Addresses and machine code are hexadecimal numbers address machine code assembly language L3: lw x2,(x) addi x,x, nop 45c c686b3 add x3,x3,x2 46 a5a733 slt x4,x,x nop nop 46c fe72e3 beq x4,x,l3 47 ce3 addi x28,x, de93 addi x29,x, ef3 addi x3,x,3 47c ff93 addi x3,x,3 What to Hand In Hand in nicely organized answers to questions 7 in What to Do