Chapter 8 VHDL Code Examples

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Elwin Shaw
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1 APPENDIX I Chapter 8 VHDL Code Examples I.1 Introduction Two example VHDL code designs are presented in Chapter 8, the first for controlling the AD7524 digital-to-analogue converter and the second for controlling an example thyristor. This appendix presents the code examples along with commenting to support the presented code: Figure 8.18 VHDL code for DAC controller Figure 8.19 Figure 8.55 Figure 8.56 VHDL test bench for DAC controller Thyristor gate control pulse generator Thyristor gate control pulse generator test bench

2 2 Appendix I I.2 VHDL Code Examples ENTITY AD7524_Controller IS PORT ( Clock : IN STD_LOGIC; Reset : IN STD_LOGIC; Data_In : IN STD_LOGIC_VECTOR (7 downto 0); Data_Out : OUT STD_LOGIC_VECTOR (7 downto 0); CS : OUT STD_LOGIC; WR : OUT STD_LOGIC); END ENTITY AD7524_Controller; ARCHITECTURE Behavioural OF AD7524_Controller IS SIGNAL Count : STD_LOGIC_VECTOR(2 downto 0); SIGNAL Update : STD_LOGIC; PROCESS (Update, Reset, Data_In) If (Reset = '0') Then Data_Out(7 downto 0) <= " "; ElsIf (Update'event and Update = '1') Then Data_Out(7 downto 0) <= Data_In(7 downto 0); PROCESS (Clock, Reset) If (Reset = '0') Then Count(2 downto 0) <= "000"; ElsIf (Clock'event and Clock = '1') Then PROCESS (Count) If (Count = "100") Then Count <= "000"; Count <= Count + 1; If (Count = "000") Then Update <='0'; CS <= '1'; WR <= '1'; ElsIf (Count = "001") Then Update <='1'; CS <= '1'; WR <= '1'; ElsIf (Count = "010") Then Update <='0'; CS <= '0'; WR <= '1'; ElsIf (Count = "011") Then Update <='0'; CS <= '0'; WR <= '0'; ElsIf (Count = "100") Then Update <='0'; CS <= '0'; WR <= '1'; Update <='0'; CS <= '1'; WR <= '1'; Figure 8.18: VHDL code for DAC controller

3 Chapter 8 VHDL Code Examples 3 ENTITY Test_AD7524_Controller_vhd IS END Test_AD7524_Controller_vhd; ARCHITECTURE Behavioural OF Test_AD7524_Controller_vhd IS COMPONENT AD7524_Controller PORT( Clock : IN STD_LOGIC; Reset : IN STD_LOGIC; Data_In : IN STD_LOGIC_VECTOR (7 downto 0); Data_Out : OUT STD_LOGIC_VECTOR (7 downto 0); CS : OUT STD_LOGIC; WR : OUT STD_LOGIC); END COMPONENT; SIGNAL Clock : STD_LOGIC := '0'; SIGNAL Reset : STD_LOGIC := '0'; SIGNAL Data_In : STD_LOGIC_VECTOR (7 downto 0) := (others=>'0'); SIGNAL Data_Out : STD_LOGIC_VECTOR(7 downto 0); SIGNAL CS : STD_LOGIC; SIGNAL WR : STD_LOGIC; uut: AD7524_Controller PORT MAP( Clock => Clock, Reset => Reset, Data_In => Data_In, Data_Out => Data_Out, CS => CS, WR => WR); Reset_Process : PROCESS Wait for 0 ns; Reset <= '0'; Wait for 5 ns; Reset <= '1'; Wait; Clock_Process : PROCESS Wait for 0 ns; Clock <= '0'; Wait for 10 ns; Clock <= '1'; Wait for 10 ns; Clock <= '0'; Figure 8.19: VHDL test bench for DAC controller

4 4 Appendix I ENTITY Pulse_Generator is PORT ( Master_Clock : IN STD_LOGIC; Master_Reset : IN STD_LOGIC; Gate_Control : OUT STD_LOGIC); END ENTITY Pulse_Generator; ARCHITECTURE Behavioural OF Pulse_Generator IS SIGNAL Divider : STD_LOGIC_VECTOR(15 downto 0); SIGNAL Int_Clock : STD_LOGIC; SIGNAL Count : STD_LOGIC_VECTOR(4 downto 0); PROCESS(Master_Clock, Master_Reset) If (Master_Reset = '0') Then Divider(15 downto 0) <= " "; ElsIf (Master_Clock'event and Master_Clock = '1') Then If (Divider = " ") Then Divider(15 downto 0) <= " "; Divider(15 downto 0) <= Divider(15 downto 0) + 1; PROCESS(Divider) If (Divider = " ") Then Int_Clock <= '1'; Int_Clock <= '0'; PROCESS(Int_Clock, Master_Reset) Figure 8.55: Thyristor gate control pulse generator

5 Chapter 8 VHDL Code Examples 5 If (Master_Reset = '0') Then Count(4 downto 0) <= "00000"; ElsIf (Int_Clock'event and Int_Clock = '1') Then If (Count = "10011") Then Count(4 downto 0) <= "00000"; Count(4 downto 0) <= Count(4 downto 0) + 1; PROCESS(Count) If (Count = "00001") Then Gate_Control <= '1'; Gate_Control <= '0'; Figure 8.55: (Continued)

6 6 Appendix I ENTITY Test_Pulse_Generator_vhd IS END Test_Pulse_Generator_vhd; ARCHITECTURE Behavioural OF Test_Pulse_Generator_vhd IS COMPONENT Pulse_Generator PORT( Master_Clock : IN STD_LOGIC; Master_Reset : IN STD_LOGIC; Gate_Control : OUT STD_LOGIC); END COMPONENT; SIGNAL Master_Clock : STD_LOGIC := '0'; SIGNAL Master_Reset : STD_LOGIC := '0'; SIGNAL Gate_Control : STD_LOGIC; uut: Pulse_Generator PORT MAP( Master_Clock => Master_Clock, Master_Reset => Master_Reset, Gate_Control => Gate_Control); Master_Reset_Process : PROCESS Wait for 0 ns; Master_Reset <= '0'; Wait for 5 ns; Master_Reset <= '1'; Wait; Master_Clock_Process : PROCESS Wait for 0 ns; Master_Clock <= '0'; Wait for 10 ns; Master_Clock <= '1'; Wait for 10 ns; Master_Clock <= '0'; Figure 8.56: Thyristor gate control pulse generator test bench

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