ECE 545 Lecture 4. Simple Testbenches. George Mason University
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1 ECE 545 Lecture 4 Simple Testbenches George Mason University
2 Required reading P. Chu, RTL Hardware Design using VHDL Chapter 2.2.4, Testbenches 2
3 Testbenches ECE 448 FPGA and ASIC Design with VHDL 3
4 Testbench Defined Testbench = VHDL entity that applies stimuli (drives the inputs) to the Design Under Test (DUT) and (optionally) verifies expected outputs. The results can be viewed in a waveform window or written to a file. Since Testbench is written in VHDL, it is not restricted to a single simulation tool (portability). The same Testbench can be easily adapted to test different implementations (i.e. different architectures) of the same design. 4
5 Simple Testbench Processes Generating Stimuli Design Under Test (DUT) Observed Outputs 5
6 Possible sources of expected results used for comparison Testbench Representative Inputs VHDL Design Manual Calculations or Reference Software Implementation (C, Java, Matlab ) actual results =? expected results 6
7 Testbench The same testbench can be used to test multiple implementations of the same circuit (multiple architectures) testbench design entity Architecture 1 Architecture Architecture N 7
8 Testbench Anatomy ENTITY my_entity_tb IS --TB entity has no ports END my_entity_tb; ARCHITECTURE behavioral OF tb IS --Local signals and constants COMPONENT TestComp --All Design Under Test component declarations PORT ( ); END COMPONENT; BEGIN DUT:TestComp PORT MAP( -- Instantiations of DUTs ); testsequence: PROCESS END PROCESS; -- Input stimuli END behavioral; 8
9 Testbench for XOR3 (1) LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY xor3_tb IS END xor3_tb; ARCHITECTURE behavioral OF xor3_tb IS -- Component declaration of the tested unit COMPONENT xor3 PORT( A : IN STD_LOGIC; B : IN STD_LOGIC; C : IN STD_LOGIC; Result : OUT STD_LOGIC ); END COMPONENT; -- Stimulus signals - signals mapped to the input and inout ports of tested entity SIGNAL test_vector: STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL test_result : STD_LOGIC; 9
10 Testbench for XOR3 (2) BEGIN UUT : xor3 PORT MAP ( A => test_vector(2), B => test_vector(1), C => test_vector(0), Result => test_result); ); Testing: PROCESS BEGIN test_vector <= "000"; test_vector <= "001"; test_vector <= "010"; test_vector <= "011"; test_vector <= "100"; test_vector <= "101"; test_vector <= "110"; test_vector <= "111"; END PROCESS; END behavioral; 10
11 VHDL Design Styles VHDL Design Styles dataflow structural behavioral Concurrent statements Components and interconnects Sequential statements Testbenches 11
12 Process without Sensitivity List and its use in Testbenches ECE 448 FPGA and ASIC Design with VHDL 12
13 What is a PROCESS? A process is a sequence of instructions referred to as sequential statements. The keyword PROCESS A process can be given a unique name using an optional LABEL This is followed by the keyword PROCESS The keyword BEGIN is used to indicate the start of the process All statements within the process are executed SEQUENTIALLY. Hence, order of statements is important. A process must end with the keywords END PROCESS. Testing: PROCESS BEGIN test_vector<= 00 ; test_vector<= 01 ; test_vector<= 10 ; test_vector<= 11 ; END PROCESS; 13
14 Execution of statements in a PROCESS The execution of statements continues sequentially till the last statement in the process. After execution of the last statement, the control is again passed to the beginning of the process. Testing: PROCESS BEGIN test_vector<= 00 ; test_vector<= 01 ; test_vector<= 10 ; test_vector<= 11 ; END PROCESS; Order of execution Program control is passed to the first statement after BEGIN 14
15 PROCESS with a WAIT Statement The last statement in the PROCESS is a WAIT instead of WAIT FOR 10 ns. This will cause the PROCESS to suspend indefinitely when the WAIT statement is executed. This form of WAIT can be used in a process included in a testbench when all possible combinations of inputs have been tested or a non-periodical signal has to be generated. Testing: PROCESS BEGIN test_vector<= 00 ; test_vector<= 01 ; test_vector<= 10 ; test_vector<= 11 ; WAIT; END PROCESS; Order of execution Program execution stops here 15
16 WAIT FOR vs. WAIT WAIT FOR: waveform will keep repeating itself forever WAIT : waveform will keep its state after the last wait instruction. 16
17 Specifying time in VHDL ECE 448 FPGA and ASIC Design with VHDL 17
18 Time values (physical literals) - Examples 7 ns 1 min min us fs unit of time most commonly used in simulation Numeric value Space (required) Unit of time 18
19 Units of time Unit Definition Base Unit fs Derived Units ps femtoseconds (10-15 seconds) picoseconds (10-12 seconds) ns nanoseconds (10-9 seconds) us microseconds (10-6 seconds) ms miliseconds (10-3 seconds) sec seconds min minutes (60 seconds) hr hours (3600 seconds) 19
20 Simple Testbenches ECE 448 FPGA and ASIC Design with VHDL 20
21 Generating selected values of one input SIGNAL test_vector : STD_LOGIC_VECTOR(2 downto 0); BEGIN... testing: PROCESS BEGIN test_vector <= "000"; test_vector <= "001"; test_vector <= "010"; test_vector <= "011"; test_vector <= "100"; END PROCESS;... END behavioral; 21
22 Generating all values of one input SIGNAL test_vector : STD_LOGIC_VECTOR(3 downto 0):="0000"; BEGIN... testing: PROCESS BEGIN test_vector <= test_vector + 1; end process TESTING;... END behavioral; 22
23 Arithmetic Operators in VHDL (1) To use basic arithmetic operations involving std_logic_vectors you need to include the following library packages: LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; or USE ieee.std_logic_signed.all; 23
24 Arithmetic Operators in VHDL (2) You can use standard +, - operators to perform addition and subtraction: signal A : STD_LOGIC_VECTOR(3 downto 0); signal B : STD_LOGIC_VECTOR(3 downto 0); signal C : STD_LOGIC_VECTOR(3 downto 0); C <= A + B; 24
25 Different ways of performing the same operation signal count: std_logic_vector(7 downto 0); You can use: count <= count ; or count <= count + 1; or count <= count + 1 ; 25
26 Different declarations for the same operator Declarations in the package ieee.std_logic_unsigned: function + ( L: std_logic_vector; R:std_logic_vector) return std_logic_vector; function + ( L: std_logic_vector; R: integer) return std_logic_vector; function + ( L: std_logic_vector; R:std_logic) return std_logic_vector; 26
27 Operator overloading Operator overloading allows different argument types for a given operation (function) The VHDL tools resolve which of these functions to select based on the types of the inputs This selection is transparent to the user as long as the function has been defined for the given argument types. 27
28 Generating all possible values of two inputs SIGNAL test_ab : STD_LOGIC_VECTOR(1 downto 0); SIGNAL test_sel : STD_LOGIC_VECTOR(1 downto 0); BEGIN... double_loop: PROCESS BEGIN test_ab <="00"; test_sel <="00"; for I in 0 to 3 loop for J in 0 to 3 loop wait for 10 ns; test_ab <= test_ab + 1; end loop; test_sel <= test_sel + 1; end loop; END PROCESS;... END behavioral; 28
29 Generating periodical signals, such as clocks CONSTANT clk1_period : TIME := 20 ns; CONSTANT clk2_period : TIME := 200 ns; SIGNAL clk1 : STD_LOGIC; SIGNAL clk2 : STD_LOGIC := 0 ; BEGIN... clk1_generator: PROCESS clk1 <= 0 ; WAIT FOR clk1_period/2; clk1 <= 1 ; WAIT FOR clk1_period/2; END PROCESS; clk2 <= not clk2 after clk2_period/2;... END behavioral; 29
30 Generating one-time signals, such as resets CONSTANT reset1_width : TIME := 100 ns; CONSTANT reset2_width : TIME := 150 ns; SIGNAL reset1 : STD_LOGIC; SIGNAL reset2 : STD_LOGIC := 1 ; BEGIN... reset1_generator: PROCESS reset1 <= 1 ; WAIT FOR reset_width; reset1 <= 0 ; WAIT; END PROCESS; reset2_generator: PROCESS WAIT FOR reset_width; reset2 <= 0 ; WAIT; END PROCESS;... END behavioral; 30
31 Typical error SIGNAL test_vector : STD_LOGIC_VECTOR(2 downto 0); SIGNAL reset : STD_LOGIC; BEGIN... generator1: PROCESS reset <= 1 ; WAIT FOR 100 ns reset <= 0 ; test_vector <="000"; WAIT; END PROCESS; generator2: PROCESS WAIT FOR 200 ns test_vector <="001"; WAIT FOR 600 ns test_vector <="011"; END PROCESS;... END behavioral; 31
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