Introduction to VHDL #3

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Britton Nicholson
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1 ECE 322 Digital Design with VHDL Introduction to VHDL #3 Lecture 7 & 8

2 VHDL Modeling Styles VHDL Modeling Styles Dataflow Concurrent statements Structural Components and interconnects Behavioral (sequential) Sequential statements Registers State machines Decoders

3 VHDL Modeling Styles-Dataflow Modeling Dataflow modeling- describes how data moves through the system and the various processing steps. Dataflow uses series of concurrent statements Dataflow is the most useful style to describe combinational logic Dataflow code also called concurrent code Concurrent statements are evaluated at the same time; thus, the order of these statements doesn t matter. This is not true for sequential/behavioral statements!

4 VHDL Modeling Styles-Dataflow Modeling Example: XOR3 These two orders are the same U1 <= A XOR B; Result <= U1 XOR C; Result <= U1 XOR C; U1 <= A XOR B;

5 VHDL Modeling Styles-Dataflow Modeling Example: XOR3 LIBRARY ieee; USE ieee.std_logic_1164.all; entity xor3_gate is port( A,B,C : in std_logic; Result : out std_logic); end xor3_gate; Architecture dataflow of xor3_gate is signal U1 : std_logic; begin U1 <= A xor B; Results <= U1 xor C; end dataflow;

6 VHDL Modeling Styles-Structural Modeling Structural design is the simplest to understand. This style is the closest to schematic capture and utilizes simple building blocks to compose logic functions. Components are interconnected in a hierarchical manner. Structural descriptions may connect simple gates or complex, abstract components. Structural style is useful when expressing a design that is naturally composed of sub-blocks.

7 VHDL Modeling Styles-Behavioral Modeling Behavioral modeling describes the function or expected behavioral of the design in an algorithmic manner This style is the closest to a natural language description of the circuit functionality Usually described using process block statements which encapsulate collections of actions executed in sequence

8 VHDL Modeling Styles-Behavioral Modeling Process block Syntax Process_label : process (sensitivity list) -- declarations Begin -- sequential statements The first line of the process statement includes a label, the keyword process, and an optional list of signals, known as the sensitivity list.

9 VHDL Modeling Styles-Behavioral Modeling A process with a sensitivity list is evaluated during simulation whenever an event occurs on any of the signals in the sensitivity list (and only then). If a process has no sensitivity list then it is evaluated when an event occurs on any signal. Process_label : process (sensitivity list) -- declarations Begin -- sequential statements

10 VHDL Modeling Styles-Behavioral Modeling Sensitivity lists are only used for speeding up simulations. They are ignored by synthesis programs. Why? Hardware synthesis needs to know about all signals, not just the active ones. Simulation, on the other hand, only needs to know about active signals.

11 VHDL Modeling Styles-Behavioral Modeling In a typical circuit application, a process will include in its sensitivity list all inputs that have asynchronous behavior. These asynchronous inputs may include: clock signal(s) reset signals inputs to blocks of combinational logic Synchronous inputs should not be listed in the sensitivity list! count or register load enable signals external control input signals

12 VHDL Modeling Styles-Behavioral Modeling Example of a sensitivity list: 3-input AND gate AND3_1 : process (A,B,C) In purely combinational circuits, all inputs are considered to be asynchronous and should therefore appear in the sensitivity list. Note: Outputs do not show up in sensitivity lists.

13 VHDL Modeling Styles-Behavioral Modeling The main part of the process block involves a set of sequential statements, delimited by begin and end Process_label : process (sensitivity list) -- declarations Begin -- sequential statements The order of the sequential statements is important! Statements inside a process block are evaluated in sequence from first to last.

14 VHDL Modeling Styles-Behavioral Modeling Types of sequential statements that can be used in process blocks: simple signal assignment statements if/then/else case for loop while loop Note: the last 4 structures can be used only inside process blocks

15 VHDL Modeling Styles-Behavioral Modeling NOTE!!! You cannot have Component instantiations Selected Signal assignments Conditional Signal assignments in process blocks!

16 If/Then/Else statements if first_condition then --statements elsif second_condition then --statements else --statements end if; The elsif and else are optional. The conditions specified in an if-then-else construct must evaluate to a Boolean signal type.

17 If/Then/Else statements Example: 3_input OR gate OR3_1 : process(a,b,c) begin F <= 0 ; if A = 1 then F <= 1 ; elsif B = 1 then F <= 1 ; elsif C = 1 then F <= 1 ; end if;

18 If/Then/Else statements Notice that there are multiple assignments to the signal F. This is allowed! multiple signal assignments OR3_1 : process(a,b,c) begin F <= 0 ; if A = 1 then F <= 1 ; elsif B = 1 then F <= 1 ; elsif C = 1 then F <= 1 ; end if;

19 If/Then/Else statements Multiple signal assignments are permitted within a process block (and only within a process block) The last assignment to be evaluated in the sequential evaluation of the statements in the process block is the one that takes effect.

20 If/Then/Else statements The first statement in the process block of the example is there to prevent the occurrence of implied memory. if not present, the circuit would hold the value of F when A=B=C=0 OR3_1 : process(a,b,c) begin F <= 0 ; if A = 1 then F <= 1 ; elsif B = 1 then F <= 1 ; elsif C = 1 then F <= 1 ; end if;

21 If/Then/Else statements It is better to provide default values for combinational outputs rather than using an ending else clause as it is easier to read and less prone to error. OR3_1 : process(a,b,c) begin if A = 1 then F <= 1 ; elsif B = 1 then F <= 1 ; elsif C = 1 then F <= 1 ; else F <= 0 ; end if; Not a good approach!

22 VHDL Modeling Styles-Behavioral Modeling You can have multiple process blocks, so - Divide your circuit into a number of functional blocks (like components) and use a separate process block to describe each one. A B C blk1 blk2 Z X blk3 Y Q

23 VHDL Modeling Styles-Behavioral Modeling blk1 : process(a,b,c) -- 2 input OR and AND gates begin X <= A or B; Y <= C and B; blk2 : process(x,y,a) -- 3 input OR gate begin Z <= X or Y or A; blk3 : process(z,b) -- implement a latch begin if Z = 1 then Q <= B; end if;

24 VHDL Modeling Styles-Behavioral Modeling The following VHDL code is incorrect. WHY? Architecture EX1 of DSD is Signal A,B,X,Y,Z : std_logic; Begin process(x,y,a) begin Z <= X or Y or A; Y <= X and A; process(z,b) begin if Z = 1 then Y <= B; end if;

25 VHDL Modeling Styles-Behavioral Modeling The code on the previous slide is in error because there is more than 1 assignment to the signal Y outside of a process block! process(x,y,a) multiple signal assignments begin Z <= X or Y or A; Y <= X and A; blk3 : process(z,b) begin if Z = 1 then Y <= B; end if;

26 VHDL Modeling Styles-Behavioral Modeling You can have multiple assignments to a signal within a process block, since only one assignment actually takes effect. This is not true outside of a process block! In effect, the multiple assignments in a process count as a single concurrent assignment statement.

27 Case Statements Case statements are a type of control statement that can be used as alternatives to if-then-else constructs. case control_expression is when test_expression1 => -- statements when test_expression2 => -- statements when others -- statements end case; The two test expressions are allowed to be true at the same time. Case statements must also include all possible conditions of the control expression. (The others expression can be used to guarantee that all conditions are covered.)

28 Case Statements The case statement is much like the selected signal assignment statement. Their syntax is different however, so be careful to use the appropriate one. Inside process block - case statements Outside process block - selected assignment

29 Case Statements entity MUX4_1 is port ( i0,i1,i2,i3 : in std_logic; sel : in std_logic_vector(1 downto 0); bitout : out std_logic); end MUX4_1; architecture Behavioral of MUX4_1 is begin process(i0,i1,i2,i3,sel) begin case sel is when "00" => bitout <= i0; when "01" => bitout <= i1; when "10" => bitout <= i2; when others => bitout <= i3; end case; end Behavioral;

Lecture 4. VHDL Fundamentals. George Mason University

Lecture 4. VHDL Fundamentals. George Mason University Lecture 4 VHDL Fundamentals George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapter 3, Basic Language Constructs of VHDL 2 Design Entity ECE 448 FPGA and ASIC Design with