The University of Alabama in Huntsville Electrical and Computer Engineering CPE/EE 422/522 Spring 2005 Homework #6 Solution
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1 5.3(a)(2), 5.6(c)(2), 5.2(2), 8.2(2), 8.8(2) The University of Alabama in Huntsville Electrical and Computer Engineering CPE/EE 422/522 Spring 25 Homework #6 Solution 5.3 (a) For the following SM chart: Draw a timing chart that shows the clock, the state (S, S or S2), the inputs (X, X2 and X3) and the outputs. The input sequence is X X2 X3 =,,,,,,. Assume that all state changes occur on the rising edge of the clock, and the inputs change on the falling edge of the clock. S/ X 2 Z X Z 2 S/ Z CLK X X2 Z 3 X 3 X 2 X3 STATE S S2 S S2 S S2 S S S2/Z X Z Z2 Z3 5.6(c) For the given SM chart: Write a VHDL description of the system. S/ X X2 Z S/Z3 S2/ X3 X4 Z2 Z3 X4
2 library ieee; use ieee.std_logic_64.all; entity SM_CHART5_6 is port (X, X2, X3, X4, X5 : in std_logic; Z, Z2, Z3 : out std_logic; CLK, RESET : in std_logic); end SM_CHART5_6; architecture BEHAVE of SM_CHART5_6 is type STATE_TYPE is (S, S, S2); signal STATE, NEXT_STATE : STATE_TYPE; process(x, X2, X3, X4, X5, STATE) Z <= ''; Z2 <= ''; Z3 <= ''; case STATE is when S => if (X = '') then NEXT_STATE <= S; if (X2 = '') then Z <= ''; NEXT_STATE <= S; when S => Z3 <= ''; if (X3 = '') then Z2 <= ''; NEXT_STATE <= S; when S2 => if (X4 = '') then if (X5 = '') then NEXT_STATE <= S; Z3 <= ''; NEXT_STATE <= S; process(clk, RESET) if (RESET = '') then STATE <= S; elsif (CLK = '' and CLK'event) then STATE <= NEXT_STATE; end BEHAVE;
3 5.2 The block diagram for an elevator controller for a building with two floors is shown below. The inputs FB and FB2 are floor buttons in the elevator. The inputs CALL and CALL2 are call buttons in the hall. The inputs FS and FS2 are floor switches that output a when the elevator is at the first or second floor landing. Outputs and control the motor, and the elevator is stopped when = =. N and are flip-flops that indicate when the elevator is needed on the first or second floor. R and R2 are signals that reset these flip-flops. DO = causes the door to open, and = indicates that the door is closed. Draw an SM chart for the elevator controller (four states). FB CALL Storage N R2 R FB2 CALL2 Storage Elevator Control FS FS2 DO Door Mechanism F2/ F2/ FS2 FS R2, DO R, DO F22/ F/ R2, DO N R, DO N
4 8.2 Design an address decoder. One input to the address decoder is an 8-bit address, which can have any range with a length of 8, for example: std_logic_vector addr(8 to 5). The second input is check : std_logic_vector(5 down to ). The address decoder will output Sel = if the upper 6 bits of the 8-bit address match the 6-bit check vector. For example, if addr = and check = -- then Sel =. Only the 6 leftmost bits of addr will be compared; the remaining bits are ignored. An - in the check vector is a don t care. library ieee; use ieee.std_logic_64.all; entity address_decoder is port (ADDRESS : in std_logic_vector; CHECK : in std_logic_vector(5 downto ); SEL : out std_logic); end ADDRESS_DECODER; architecture BEHAV of ADDRESS_DECODER is alias ADDR : std_logic_vector(address'length- downto ) is ADDRESS; process(address, CHECK) variable MATCH : boolean; MATCH := TRUE; for I in ADDRESS'length- downto ADDRESS'length--5 loop if ((ADDR(I) /= CHECK(I-2)) and (CHECK(I-2) /= '-')) then MATCH := FALSE; end loop; if (MATCH) then SEL <= ''; SEL <= ''; end BEHAV; 8.8 Write a VHDL function to compare two IEEE std_logic_vectors to see whether they are equal. Report an error if any bit in either vector is not,, or - (don t care), or if the lengths of the vector are not the same. The function call should pass only the vectors. The function should return TRUE if the vectors are equal, FALSE. When comparing the vectors, consider that = - and = -. Make no assumptions about the index range of the two vectors. library ieee; use ieee.std_logic_64.all; package MINE is function "=" (L, R : std_logic_vector) return boolean; end MINE;
5 package body MINE is function "=" (L, R : std_logic_vector) return boolean is variable EQUAL : boolean; alias LEFT : std_logic_vector(l'length- downto ) is L; alias RIGHT : std_logic_vector(l'length- downto ) is R; assert L'length = R'length report "Vectors are not the same length" EQUAL := TRUE; for I in LEFT'range loop case LEFT(I) is when '' => case RIGHT(I) is when '' '-' => null; when '' => case RIGHT(I) is when '' '-' => null; when '-' => case RIGHT(I) is when '' '' => null; when others => assert FALSE report "First vector has invalid value" assert (RIGHT(I)='' or RIGHT(I)='' or RIGHT(I)='-') report "Second vector has invalid value" end loop; return EQUAL; end "="; end MINE;
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