Hardware Description Languages. Modeling Complex Systems

Transcription

1 Hardware Description Languages Modeling Complex Systems 1

2 Outline (Raising the Abstraction Level) The Process Statement if-then, if-then-else, if-then-elsif, case, while, for Sensitivity list Signals vs. Variables Behavior Concurrent processes The Wait statement wait until, wait for, wait on, wait Attributes Modeling State Machines 2

3 Raising the Level of Abstraction Data Output Data input Address R W Memory Module add R1, R2, R3 sub R3, R4, R5 move R7, R3. Instruction Set Simulation CSA statements can easily capture the gate level behavior of digital systems But, higher level digital components have complex behaviors Input/output behavior is not easy to describe at gate level Models may utilize state information Incorporate data structures We need more powerful constructs!!! 3

4 Extending the Event Computation Model Input signals Description of a Complex Process Sig1 <=.. Sig2 <=... Output signals Combinational logic input/output semantics Events on inputs causes re-computation Re-computation may lead to events on outputs Computation of the value and time of output events can be a complex process 4

5 The Process Statement library IEEE; use IEEE.std_logic_1164.all; entity mux4 is port (in0, in1, in2, in3: in std_logic_vector(7 downto 0); sel: in std_logic_vector(1 downto 0); z : out std_logic_vector(7 downto 0)); end entity mux4; architecture behavioral of mux4 is Sensitivity List process (sel, in0, in1, in2, in3) is variable zout: std_logic; Use of variables rather than signals if (Sel = 00 ) then zout := in0; elsif (Sel = 01 ) then Zout := in1; Variable Assignment elsif (Sel = 10 ) then Zout := in2; else Zout:= in3; end if; z <= zout; end process; end architecture behavioral; 5

6 Process Statement Mechanisms Statements in a process are executed sequentially A process body is structured much like conventional C function Declaration and use of variables if-then, if-then-else, case, for and while constructs A process can contain signal assignment statements A process executes concurrently with other processes and other CSA statements. A process takes 0 seconds of simulated time to execute and may schedule events on signals in the future We can think of a process as a big CSA statement! 6

7 Using Concurrent Processes: Full Adder Example In1 In2 Half Adder s1 Half Adder s2 sum c_in c_out s3 port Internal signal Model using processes Each of the components of the full adder can be modeled using a process Processes execute concurrently Processes communicate via signals 7

8 Using Concurrent Processes: Full Adder Example library IEEE; use IEEE.std_logic_1164.all; entity full_adder is port (in1, c_in, in2: in std_logic; sum, c_out : out std_logic); end entity full_adder; architecture beh of full_adder is signal s1, s2, s3: std_logic; HA1: process (in1, in2) is s1 <= (In1 xor In2); s3 <= (In1 and In2); end process HA1; HA2: process(s1,c_in) is sum <= (s1 xor c_in); s2 <= (s1 and c_in); end process HA2; OR1: process (s2, s3) is -- process describing the -- two-input OR gate c_out <= (s2 or s3); end process OR1; end architecture beh; 8

9 Using Concurrent Processes: Half Adder Example library IEEE; use IEEE.std_logic_1164.all; entity half_adder is port (a, b : in std_logic; sum, carry : out std_logic); end entity half_adder; architecture behavior of half_adder is sum_proc: process(a,b) is if (a = b) then sum <= 0 ; else sum <= (a or b); end if; end process; carry_proc: process (a,b) is case a is when 0 => carry <= a; when 1 => carry <= b; when others => carry <= X ; end case; end process carry_proc; end architecture behavior; 9

10 Processes + CSAs: Example MemRead MemWrite library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; address write_data read_data entity memory is port (address, write_data: in std_logic_vector (7 downto 0); MemWrite, MemRead, clk, reset: in std_logic; read_data: out std_logic_vector (7 downto 0)); end entity memory; architecture behavioral of memory is signal dmem0,dmem1,dmem2,dmem3: std_logic_vector (7 downto 0); mem_proc: process (rising_edge(clk)) is -- code process body here end process mem_proc; -- code read operation CSA here end architecture behavioral; clk reset 10

11 Process + CSAs: The MemWrite Process mem_proc: process (clk) is if (rising_edge(clk)) then -- wait until next clock edge if reset = 1 then -- initialize values on reset dmem0 <= x 00 ; -- memory locations are initialized to dmem1 <= x 11 ; -- some random values dmem2 <= x 22 ; dmem3 <= x 33 ; elsif MemWrite = 1 then -- if not reset then check for memory write case address (1 downto 0) is when 00 => dmem0 <= write_data; when 01 => dmem1 <= write_data; when 10 => dmem2 <= write_data; when 11 => dmem3 <= write_data; when others => dmem0 <= x ff ; end case; end if; end if; end process mem_proc; 11

12 Process + CSAs: The MemRead Statement -- memory read is implemented with a conditional signal assignment read_data <= dmem0 when address (1 downto 0) = 00 and MemRead = 1 else dmem1 when address (1 downto 0) = 01 and MemRead = 1 else dmem2 when address (1 downto 0) = 10 and MemRead = 1 else dmem3 when address (1 downto 0) = 11 and MemRead = 1 else x 00 ; A process can be viewed as single CSA statement The external behavior is the same as a CSA Processes describe more complex event generation behavior Processes execute concurrently with other CSAs 12

13 Iteration statements There are two iterations statements: For loop While loop 13

14 The For Loop Statement for - loop The index is implicitly declared Scope is local to the loop If a variable or signal with the same name is used elsewhere in the process or architecture (but not in the same loop) it is treated as a distinct object for index in 1 to 32 loop... end loop; 14

15 The While Loop Statement while loop Boolean expression for termination while j < 32 loop j := j+1; end loop; NOT SYNTHESIZABLE!! 15

16 More on Processes Behavior All processes are executed once at start-up After start-up only dependencies between signal values and events on these signals determine process execution Signals behave differently from variables! 16

17 Using Signals in a Process In1 s1 s3 z In2 s2 s4 Entity signals are visible in a process Processes can encapsulate variable and signal assignment statements What is the difference on the model behavior between dataflow (CSAs) and process models? 17

18 Mis-using Signals in a Process library IEEE; use IEEE.std_logic_1164.all; entity combo is port (In1, In2 : in std_logic; z: out std_logic); end entity combo; architecture beh of combo is signal s1, s2, s3, s4: std_logic; s1 <= not In1; s2 <= not In2; s3 <= not (s1 and In2); s4 <= not (s2 and In1); z <= not (s3 and s4); end architecture beh; Encapsulate in a process library IEEE; use IEEE.std_logic_1164.all; entity combo is port (In1, In2: in std_logic; z : out std_logic); end entity combo; architecture beh of combo is signal s1, s2, s3, s4: std_logic; sig_in_proc: process (In1, In2) is s1 <= not In1; s2 <= not In2; s3 <= not (s1 and In2); s4 <= not (s2 and In1); z <= not (s3 and s4); end process sig_in_proc; end architecture beh; 18

19 Mis-using Signals in a Process (cont.) IN1 IN1 IN2 IN2 Z Z S1 S1 S2 S2 S3 S3 S4 S Using CSA statements Using signal assignment statements within a process 19

20 Signals vs. Variables library IEEE; use IEEE.std_logic_1164.all; entity combo is port (In1, In2: in std_logic; z : out std_logic); end entity combo; architecture beh of combo is variable s1, s2, s3, s4: std_logic; sig_in_proc: process (In1, In2) is s1 := not In1; s2 := not In2; s3 := not (s1 and In2); s4 := not (s2 and In1); z <= not (s3 and s4); end process sig_in_proc; end architecture beh; Use variables for computing intermediate values 20

21 Signals vs. Variables -- Process 1 Correct Coding Style proc1: process (x, y, z) is variable var_s1, var_s2: std_logic; var_s1 := x and y; var_s2 := var_s1 xor z; res1 <= var_s1 nand var_s2; end process; Process 2 Incorrect proc2: process (x, y, z) is sig_s1 <= x and y; sig_s2 <= sig_s1 xor z; res2 <= sig_s1 nand sig_s2; end process; variables signals 21

22 The Wait Statement Signal Assignments suspend execution until the next event on a signal on the RHS of the assignment statement This behavior fit in well with the behavior of combinational circuits, in which a change on the input signals may cause a change in the value of the output signal What about modeling circuits for which the outputs are computed only at specific point in time, independently of event on the inputs? We need a more general manner to specify the condition under which the circuit outputs must be recomputed! This capability is provided by the wait statement 22

23 The Wait Statement The wait statement explicitly specifies the conditions under which a process may resume execution after being suspendend. There are four forms of wait statements: wait for time-expression wait on signal wait wait until condition NON SYNTHESIZABLE!! SYNTHESIZABLE!! 23

24 The Wait Statement: Waveform Generation library IEEE; use IEEE.std_logic_1164.all; entity two_phase is port(phi1, phi2, reset: out std_logic); end entity two_phase; architecture behavioral of two_phase is rproc: reset <= 1, 0 after 10 ns; clock_process: process is phi1 <= 1, 0 after 10 ns; phi2 <= 0, 1 after 12 ns, 0 after 18 ns; wait for 20 ns; end process clock_process; end architecture behavioral; events specified by the r e set and clock pr o cesses reset phi1 phi T i me (ns) Note the perpetual behavior of processes 24

25 Example of Positive Edge-Triggered DFF using the Wait Statement library IEEE; use IEEE.std_logic_1164.all; entity dff is port (D, Clk : in std_logic; Q, Qbar : out std_logic); signifies a value change on signal clk end entity dff; architecture behavioral of dff is output: process is wait until (Clk event and Clk = 1 ); -- wait for rising edge Q <= D; -- guideline: use the function Qbar <= not D; -- rising_edge(clk) end process output; end architecture behavioral; 25

26 Example of DFF with Synchronous inputs using the Wait Statement library IEEE; use IEEE.std_logic_1164.all; entity synchdff is port (R, S, D, Clk : in std_logic; Q, Qbar : out std_logic); end entity synchdff; architecture behavioral of synchdff is output: process is wait until (Clk event and Clk = 1 ); -- wait for rising edge if R = 1 then -- check for reset and initialize state Q <= 0 ; Qbar <= 1 ; elsif S= 1 then -- check for set and initialize Q <= 1 ; Qbar <= 0 ; else Q <= D; Qbar <= not(d); end if; end process output; end behavioral; 26

27 Example of DFF with Asynchronous inputs using the Wait Statement library IEEE; use IEEE.std_logic_1164.all; entity asynchdff is port (R, S, D, Clk : in std_logic; Q, Qbar : out std_logic); end entity asynchdff; architecture behavioral of asynchdff is output: process is wait until (R = '1' or S='1' or (clk'event and clk ='1')); if (R='1') then Q <= '0'; Qbar <= '1'; elsif (S='1') then Q <= '1'; Qbar <= '0'; else -- wait for rising edge Q <= D; Qbar <= not(d); end if; end process output; end behavioral; 27

28 How to avoid the use of Wait Statements: example of Positive Edge Triggered DFF library IEEE; use IEEE.std_logic_1164.all; entity dff is port (D, Clk: in std_logic; Q, Qbar: out std_logic); end entity dff; architecture behavioral of dff is output: process (Clk) is if (rising_edge(clk)) then Q <= D; Qbar <= (not D); end if; end process output; end architecture behavioral; 28

29 How to avoid the use of Wait Statements: example of DFF with Synchronous Inputs library IEEE; use IEEE.std_logic_1164.all; entity synch_dff is port (R, S, D, Clk: in std_logic; Q, Qbar: out std_logic); end entity synch_dff; architecture behavioral of synch_dff is output: process (Clk) is if (rising_edge(clk)) then if (R = 0 ) then Q <= 0; Qbar <= 1 ; elsif S = 0 then Q <= 1 ; Qbar <= 0 ; else Q <= D; Qbar <= (not D); end if; end if; end process output; end architecture behavioral; execute on event on any signal implied ordering provides asynchronous set reset 29

30 How to avoid the use of Wait Statements: example of DFF with Asynchronous Inputs library IEEE; use IEEE.std_logic_1164.all; entity asynch_dff is port (R, S, D, Clk: in std_logic; Q, Qbar: out std_logic); end entity asynch_dff; architecture behavioral of asynch_dff is output: process (R, S, Clk) is if (R = 0 ) then Q <= 0; Qbar <= 1 ; elsif S = 0 then Q <= 1 ; Qbar <= 0 ; elsif (rising_edge(clk)) then Q <= D; Qbar <= (not D); end if; end process output; end architecture behavioral; implied ordering provides asynchronous set reset execute on event on any signal 30

31 In Summary: The Wait Statement Wait statements provide explicit control over suspension and resumption of processes and can be used to represent both synchronous and asynchronous events A process can have multiple wait statements A process cannot have both a wait statement and a sensitivity list (it should have one or the other): Why? 31

32 Wait Statements style vs. Sensitivity List style Guideline: Do not use wait statements, use the sensitivity list Using wait statements, logic associated with each clock has to be described in a different process, and synchronous logic has to be separated from combinational logic. 32

33 In Summary: The Process Statement A process statement is a concurrent statement, but all statements contained in it are sequential statement (statements that executes serially, one after another). The use of processes allows to raise the level of abstraction (support advanced language constructs) usable, makes your code more modular, more readable, and allows you to separate combinational logic from sequential logic. 33

34 In Summary: The sensitivity list List of all signals that the process is sensitive to. Sensitive means that a change in the value of these signals will cause the process to be invoked. 34

35 For Combinational Logic: the sensitivity list must be complete!!! process (a) variable a_or_b; begin a_or_b := a or b; z <= a_or_b; end process; -- since b is not in the -- sensitivity list, when -- a change occurs on b -- the process is not -- invoked, so the value -- of z is not updated -- (still remembering the -- old value of z) 35

36 Combinational Logic: incomplete sensitivity list effect a b z z (VHDL) (gate level) 36

37 For Combinational Logic: What to put in sensitivity list? All signals you do a test on and all signals that are on the right side of an assignment. In other words all the signals you are reading in the value Don t read and write a signal at the same time!!! 37

38 Bad coding example: delta time issues!!! write architecture bad of logic is signal a_or_b : std_logic; begin logic_p: process(a,b,c) begin a_or_b <= a or b; z <= a_or_b and c; end process; end bad; read Do not read and write a signal at the same time!!! 38

39 How to fix the bad coding example architecture good of logic is variable a_or_b : std_logic; begin logic_p: process(a,b,c) begin a_or_b := a or b; z <= a_or_b and c; end process; end good; 39

40 Predefined Attributes Value attributes returns a constant value Function attributes invokes a function that returns a value Signal attributes creates a new signal Type Attributes Supports queries about the type of VHDL objects (Advanced Topic: Let s procrastinate for now ) Range attributes returns a range 40

41 Value Attributes Return a constant value Examples: type state_type is (state0, state1, state2, state3); state_type left = state0 state_type right = state3 Value attribute type_name left type_name right type_name high type_name low array_name length Value returns the leftmost value of type_name returns the rightmost value of type_name returns the largest value of type_name returns the smallest value of type_name returns the number of elements in array_name 41

42 More examples on value attributes 42

43 More examples on value attributes (cont.) 43

44 Function Attributes Function attributes invoke a function call which returns a value Examples: if (Clk event and Clk = 1 ) Function attribute signal_name event signal_name active Function Return a Boolean value signifying a change in value on this signal Return a Boolean value signifying an assignment made to this signal. This assignment may not be a new value. signal_name last_event Return the time since the last event on this signal signal_name last_active Return the time since the signal was last active signal_name last_value Return the previous value of this signal 44

45 Function Attributes (cont.) Examples of function array attributes Function attribute array_name left array_name right array_name high array_name low Function returns the left bound of the index range returns the right bound of the index range returns the upper bound of the index range returns the lower bound of the index range 45

46 Range Attributes Returns the index range of a constrained array variable wbus: std_logic_vector(7 downto 0); signal xbus: std_logic_vector(wbus range); 46

47 Signal Attributes Creates a new implicit signal Signal attribute signal_name delayed(t) signal_name transaction signal_name quiet(t) signal_name stable(t) Implicit Signal Signal delayed by T units of time Signal whose value toggles when signal_name is active True when signal_name has been quiet for T units of time True when event has not occurred on signal_name for T units of time Internal signals are useful modeling tools 47

48 Signal Attributes: Example architecture behavioral of attributes is outdelayed <= data'delayed(5 ns); outtransaction <= data'transaction; end attributes; These are real (in simulation) signals and can be used elsewhere in the model 48

49 Modeling State Machines Inputs Combinational logic Outputs 1/0 0/1 s0 s1 0/1 Next state 1/0 S t ate Clk Basic components Combinational component: output function and next state function Sequential component 49

50 Example: State Machine library IEEE; use IEEE.std_logic_1164.all; entity state_machine is port(reset, clk, x : in std_logic; z : out std_logic); end entity state_machine; architecture rtl of state_machine is type statetype is (state0, state1); signal state, next_state : statetype; comb_process: process (state, x) is -- process description here end process comb_process; clk_process: process (clk, reset) is -- process description here end process clk_process; end architecture rtl; 50

51 Example: Output and Next State Functions comb_process: process (state, x) is case state is -- depending upon the current state when state0 => -- set output signals and next state if x = 0 then next_state <= state1; z <= 1 ; else next_state <= state0; z <= 0 ; end if; when state1 => if x = 1 then next_state <= state0; z <= 0 ; else next_state <= state1; z <= 1 ; end if; when others => -- nothing end case; end process comb_process; Combination of the next state and output functions 51

52 Example: Clock Process clk_process: process (clk, reset) is if reset = 1 then -- check for reset and initialize state state <= statetype left; elsif (rising_edge(clk)) state <= next_state; end if; end process clk_process; end architecture rtl; Use of asynchronous reset to initialize into a known state 52

53 Summary Processes variables and sequential signal statements if-then, if-then-else, if-then-elsif, case, while, for concurrent processes sensitivity list The Wait statement wait until, wait for, wait on, wait Attributes Modeling State machines 53