EECS 470 Midterm Exam Fall 2014
|
|
- Alexis Hancock
- 6 years ago
- Views:
Transcription
1 EECS 470 Midterm Exam Fall 2014 Name: uniqname: Rewrite and sign the honor code below: I have neither given nor received aid on this exam nor observed anyone else doing so. Signature: Scores: Page # Points 2 /15 3 /5 4 /10 5 /10 6 /5 7 /15 8 /20 9 /20 Total /100 NOTES: Open book and Open notes Calculators are allowed but not if it has communication support (Bluetooth, Cell phones, etc.) Don t spend too much time on any one problem. You have about 120 minutes for the exam. Be sure to show work and explain what you ve done when asked to do so. Page 1 of 10
2 1) Fill in the blank [10 points, -1 per blank or wrong answer] a. We refer to hazards that can be resolved by forwarding as _READ_ after_write_ hazards. b. The lowest CPI (assuming no hazards) that is possible in a 5 stage pipeline is 1, while the lowest CPI in an 8 stage pipeline is 1. c. Results from instructions which have completed but not retired are found in the PRF in a MIPS R10K design and in the ROB in an Intel P6 design. d. The ROB is flushed when the retiring instruction is a(n) _MISPREDICTED BRANCH_ or EXCEPTION / INTERRUPT. e. A processor with a byte addressable, 64-bit address space and a 512 byte, 16 way associative L1 cache with 64 bit lines has 59 bits for the tag and 61 bits for the index when using single address cache lines. 2) Circle the correct answer(s). There may be multiple correct answers for each question [5 points, -1 per blank or wrong answer. Minimum of 0] a. True dependencies are also called RAW/WAW/WAR/RAR hazards. b. Hazards which can be resolved by renaming are called RAW/WAW/WAR/RAR hazards. c. The problem that multicore designs are intended to solve is area/power consumption/memory speed. d. A joule is equivalent to a (W*s)/(W/s)/(W^2). Page 2 of 10
3 3) The following is a dependency graph of a program, where each node represents an instruction and each edge represents a data dependency: Recall that ILP is the average number of instructions that can be executed in parallel. What is the ILP of the above program? Explain how you obtained the ILP number. [5 points] 7 instructions over 3 levels -> 7/3 Page 3 of 10
4 4) A program is 20% serial and the rest can be perfectly parallelized with no additional overhead. What is the maximum speed up possible with infinite resources? Show your work. [5 points] Speedup = 1/.2 = 5 5) A computer is capable of DVFS -- dynamic voltage (V) and frequency (f) scaling. Recall that power is proportional to V 2 f and f is proportional to V. If the computer runs at its maximum voltage of V max it will finish a particular task in T/2 seconds. a. What voltage should the computer run at if it is to finish the task in T seconds? b. If the amount of energy used to perform the task in the V max case is E, what is it in case describe in (a)? [5 points] a) freq is proportional to voltage. Performs half as fast, so half the voltage = (v_max/2) b) Power is reduced to (1/2)^3 = 1/8). Takes twice as long, so overall consumption is (1/8*2) = ¼ E Page 4 of 10
5 6) Verilog: a. Consider the following Verilog excerpt from ex_stage.v of the provided Verisimple Pipeline (project 3): always_comb begin case (func) ALU_MULQ: result = opa * opb; // other cases endcase end Briefly (one or two sentences), describe why you should not implement multiplication in this way for your final project. [5 points] Single cycle multiplier s critical path is too large. Use pipelined multiplier instead. b. Bruce is working on a Verilog design for 470. He is finding that the design is not working as he expects after synthesis. He thinks the problem is with the following code: always_comb begin status = 0; count = 0; case(count) 0: count = 1; 1: begin if(en_a) status = 1; count = 2; end 2: begin count = 0; if(en_b) status = 1; end endcase end Describe which synthesis guideline Bruce has violated. [5 points] Circular combinational logic. count depends on itself (no steady state value). Note that no latches are formed, since status and count are given default values. Page 5 of 10
6 7) Write a module in behavioral Verilog (i.e. do not instantiate any submodules) which implements the following device. You are to keep the signal names the same as they are in the provided figures (although you may create your own internal signals, where appropriate). Your code should be reasonably efficient. Minor syntax errors will be ignored. [5 points] module thing ( ); input A, B, C, S, output out logic top, bottom, next_top, next_bottom; assign next_top = S? B : A; assign next_bottom = S? C : top; assign out = bottom; Clk) begin end endmodule top <= next_top; bottom <= next_bottom; Page 6 of 10
7 8) a. Consider the pipeline you were to implement for your third programming assignment, but assume that the structural hazard on memory has been removed. Branches are still resolved in the memory stage. A given program consists of 30% loads, 5% stores, 15% branches and 50% ALU operations. If 30% of the branches are not-taken and 40% of all instructions are dependent on the instruction in front of them, what is the expected CPI of the processor on this program? Show your work. [5 points] Base CPI + stalls due to data dependencies (load followed by dependent) + stalls due to branch mispredicts 1 +.3*4 +.15*.7*3 = b. Sally has done some analysis on the pipeline and has realized that the front-end of the machine is much faster than the back-end of the machine. She proposes that merging the IF and ID stage into a single stage will make the machine faster. In other words, the new pipeline is a 4-stage pipeline with stages IFD, EX, MEM, WB, where IFD performs all the functionality of IF and ID in a single clock period. If the new frequency is 5% slower than the original, what is the expected speedup on the program specified in part (a)? Show your work. [10 points] New CPI = 1 +.3*4 +.15*.7*2 = 1.33 Speedup = (1.33 * 1.05) / = 1.02 Page 7 of 10
8 9) In this problem, we are using the P6 out-of-order execution scheme. Map Table ROB Head = 5 Tail = 6 Arch ROB# Buffer PC Done Dest. Value Reg. # (-- if in ARF) Number with EX? Arch Reg # Y N/A N Y Y Y N N RS RS# Op type Op1 ready? Op1 RoB/value Op2 ready? Op2 RoB/value Dest ROB 0 + Y -1 Y Y 5 Y ^ N 5 Y ARF Reg# Value Now say that the instruction in ROB #0 is a branch, which should have gone to top. top: R0=R3+R4 R2=R4<<2 R5=R1-R2 R3=R5^R3 // A // B // C // D Update the state of the machine to reflect that C has dispatched, but not issued and everything else has made as much progress as it can, given that constraint. Assume an RS entry is cleared at the beginning of execution. The PC of instruction A is 48 and each instruction is 4 bytes in size. [20 points] Page 8 of 10
9 10) Consider a processor implementing the R10K algorithm discussed in class. This processor has 32 architected registers, 64 ROB entries, 8 reservation stations, 1 CDB and 32-bit memory addresses (for both instruction and data memory). Assume for this example that there are no exceptions/interrupts, but the ROB does have to handle branch mispredicts as well as halting instructions. List all input and output that will be used to implement the ROB by filing in the table below. We ve done two signals for you as an example. Note that there is some design freedom here, so explain your reasoning for each signal. You may not need the entire table. This is a difficult question. We recommend doing it after completing the others. [20 points] There are multiple solutions, depending on the specific implementation. Below is an partial list of signals you should have Description of signal Input/ Output Why it s needed Tag in from CDB Input Need to mark when an instruction has finished execution and is ready to retire Halt in from dispatch Input Need to know if a dispatched instruction is a halt, so we can stop the program after retire How many bits? >6 1 Clock / reset Tag in dispatch Tag_old in dispatch Tag_old out Input 1/1 Input >6 Input >6 Output Update free list >6 Mispredict in Input Mark entry after Complete to flush ROB at retire 1 Flush out Output Flush pipeline at mispredict 1 Dispatch enable In Set low if no valid instruction or structural hazard 1 Page 9 of 10
10 ROB full Out Stall dispatch if necessary 1 Target PC_in In In case there s a branch mispredicts 32 Target PC_out Out // 32 Retire valid out Out 1 Halt_out Out 1 // Whatever signals you used for branch recovery Page 10 of 10
EECS 470 Midterm Exam
EECS 470 Midterm Exam Winter 2014 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: NOTES: # Points Page 2 /12 Page 3
More informationEECS 470 Midterm Exam
EECS 470 Midterm Exam Fall 2009 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: NOTES: # Points Page 2 /18 Page 3 /15
More informationEECS 470 Final Exam Fall 2005
EECS 470 Final Exam Fall 2005 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: # Points Section 1 /30 Section 2 /30
More informationEECS 470 Midterm Exam Answer Key Fall 2004
EECS 470 Midterm Exam Answer Key Fall 2004 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: # Points Part I /23 Part
More informationEECS 470 Midterm Exam Winter 2008 answers
EECS 470 Midterm Exam Winter 2008 answers Name: KEY unique name: KEY Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: #Page Points 2 /10
More informationEECS 470 Midterm Exam Winter 2015
EECS 470 Midterm Exam Winter 2015 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: Page # Points 2 /20 3 /15 4 /9 5
More informationEECS 470 Midterm Exam Fall 2006
EECS 40 Midterm Exam Fall 2 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: # Points Page 2 /18 Page 3 /13 Page 4 /15
More informationEECS 470 Final Exam Fall 2013
EECS 470 Final Exam Fall 2013 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: Page# Points 2 /21 3 /8 4 /12 5 /10 6
More informationb) Register renaming c) CDB, register file, and ROB d) 0,1,X (output of a gate is never Z)
1) a) Issuing stores to memory and (maybe) writing results back to register file (depends if we have a distinct physical register file). Instruction dispatch is usually done in program order, but can be
More informationEECS 470 Midterm Exam Winter 2009
EECS 70 Midterm Exam Winter 2009 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: # Points 1 / 18 2 / 12 3 / 29 / 21
More informationEECS 470 Lecture 7. Branches: Address prediction and recovery (And interrupt recovery too.)
EECS 470 Lecture 7 Branches: Address prediction and recovery (And interrupt recovery too.) Warning: Crazy times coming Project handout and group formation today Help me to end class 12 minutes early P3
More informationEECS 470. Branches: Address prediction and recovery (And interrupt recovery too.) Lecture 7 Winter 2018
EECS 470 Branches: Address prediction and recovery (And interrupt recovery too.) Lecture 7 Winter 2018 Slides developed in part by Profs. Austin, Brehob, Falsafi, Hill, Hoe, Lipasti, Martin, Roth, Shen,
More informationEECS 470 Final Exam Winter 2012
EECS 470 Final Exam Winter 2012 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: # Points Page 2 /11 Page 3 /13 Page
More informationEECS 470 Final Exam Fall 2015
EECS 470 Final Exam Fall 2015 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: Page # Points 2 /17 3 /11 4 /13 5 /10
More informationCS 2410 Mid term (fall 2015) Indicate which of the following statements is true and which is false.
CS 2410 Mid term (fall 2015) Name: Question 1 (10 points) Indicate which of the following statements is true and which is false. (1) SMT architectures reduces the thread context switch time by saving in
More informationEECS 470 Lecture 6. Branches: Address prediction and recovery (And interrupt recovery too.)
EECS 470 Lecture 6 Branches: Address prediction and recovery (And interrupt recovery too.) Announcements: P3 posted, due a week from Sunday HW2 due Monday Reading Book: 3.1, 3.3-3.6, 3.8 Combining Branch
More informationReorder Buffer Implementation (Pentium Pro) Reorder Buffer Implementation (Pentium Pro)
Reorder Buffer Implementation (Pentium Pro) Hardware data structures retirement register file (RRF) (~ IBM 360/91 physical registers) physical register file that is the same size as the architectural registers
More informationPage 1. Recall from Pipelining Review. Lecture 16: Instruction Level Parallelism and Dynamic Execution #1: Ideas to Reduce Stalls
CS252 Graduate Computer Architecture Recall from Pipelining Review Lecture 16: Instruction Level Parallelism and Dynamic Execution #1: March 16, 2001 Prof. David A. Patterson Computer Science 252 Spring
More informationMultiple Instruction Issue and Hardware Based Speculation
Multiple Instruction Issue and Hardware Based Speculation Soner Önder Michigan Technological University, Houghton MI www.cs.mtu.edu/~soner Hardware Based Speculation Exploiting more ILP requires that we
More informationECE 313 Computer Organization FINAL EXAM December 14, This exam is open book and open notes. You have 2 hours.
This exam is open book and open notes. You have 2 hours. Problems 1-5 refer to the following: We wish to add a new R-Format instruction to the MIPS Instruction Set Architecture called l_inc (load and increment).
More informationInstruction Frequency CPI. Load-store 55% 5. Arithmetic 30% 4. Branch 15% 4
PROBLEM 1: An application running on a 1GHz pipelined processor has the following instruction mix: Instruction Frequency CPI Load-store 55% 5 Arithmetic 30% 4 Branch 15% 4 a) Determine the overall CPI
More informationOPEN BOOK, OPEN NOTES. NO COMPUTERS, OR SOLVING PROBLEMS DIRECTLY USING CALCULATORS.
CS/ECE472 Midterm #2 Fall 2008 NAME: Student ID#: OPEN BOOK, OPEN NOTES. NO COMPUTERS, OR SOLVING PROBLEMS DIRECTLY USING CALCULATORS. Your signature is your promise that you have not cheated and will
More informationE0-243: Computer Architecture
E0-243: Computer Architecture L1 ILP Processors RG:E0243:L1-ILP Processors 1 ILP Architectures Superscalar Architecture VLIW Architecture EPIC, Subword Parallelism, RG:E0243:L1-ILP Processors 2 Motivation
More information1. Truthiness /8. 2. Branch prediction /5. 3. Choices, choices /6. 5. Pipeline diagrams / Multi-cycle datapath performance /11
The University of Michigan - Department of EECS EECS 370 Introduction to Computer Architecture Midterm Exam 2 ANSWER KEY November 23 rd, 2010 Name: University of Michigan uniqname: (NOT your student ID
More informationCMSC411 Fall 2013 Midterm 1
CMSC411 Fall 2013 Midterm 1 Name: Instructions You have 75 minutes to take this exam. There are 100 points in this exam, so spend about 45 seconds per point. You do not need to provide a number if you
More informationCS 2506 Computer Organization II Test 2. Do not start the test until instructed to do so! printed
Instructions: Print your name in the space provided below. This examination is closed book and closed notes, aside from the permitted fact sheet, with a restriction: 1) one 8.5x11 sheet, both sides, handwritten
More informationDesign of Digital Circuits ( L) ETH Zürich, Spring 2017
Name: Student ID: Final Examination Design of Digital Circuits (252-0028-00L) ETH Zürich, Spring 2017 Professors Onur Mutlu and Srdjan Capkun Problem 1 (70 Points): Problem 2 (50 Points): Problem 3 (40
More informationEECC551 Exam Review 4 questions out of 6 questions
EECC551 Exam Review 4 questions out of 6 questions (Must answer first 2 questions and 2 from remaining 4) Instruction Dependencies and graphs In-order Floating Point/Multicycle Pipelining (quiz 2) Improving
More informationComputer Architecture EE 4720 Final Examination
Name Computer Architecture EE 4720 Final Examination 7 May 2008, 10:00 12:00 CDT Alias Problem 1 Problem 2 Problem 3 Problem 4 Problem 5 Problem 6 Exam Total (10 pts) (30 pts) (20 pts) (15 pts) (15 pts)
More informationCS433 Midterm. Prof Josep Torrellas. October 19, Time: 1 hour + 15 minutes
CS433 Midterm Prof Josep Torrellas October 19, 2017 Time: 1 hour + 15 minutes Name: Instructions: 1. This is a closed-book, closed-notes examination. 2. The Exam has 4 Questions. Please budget your time.
More informationCS 2506 Computer Organization II Test 2. Do not start the test until instructed to do so! printed
Instructions: Print your name in the space provided below. This examination is closed book and closed notes, aside from the permitted fact sheet, with a restriction: 1) one 8.5x11 sheet, both sides, handwritten
More informationECE 313 Computer Organization FINAL EXAM December 13, 2000
This exam is open book and open notes. You have until 11:00AM. Credit for problems requiring calculation will be given only if you show your work. 1. Floating Point Representation / MIPS Assembly Language
More informationHardware-based Speculation
Hardware-based Speculation Hardware-based Speculation To exploit instruction-level parallelism, maintaining control dependences becomes an increasing burden. For a processor executing multiple instructions
More informationHandout 2 ILP: Part B
Handout 2 ILP: Part B Review from Last Time #1 Leverage Implicit Parallelism for Performance: Instruction Level Parallelism Loop unrolling by compiler to increase ILP Branch prediction to increase ILP
More informationCPE 631 Lecture 10: Instruction Level Parallelism and Its Dynamic Exploitation
Lecture 10: Instruction Level Parallelism and Its Dynamic Exploitation Aleksandar Milenković, milenka@ece.uah.edu Electrical and Computer Engineering University of Alabama in Huntsville Outline Tomasulo
More informationWebsite for Students VTU NOTES QUESTION PAPERS NEWS RESULTS
Advanced Computer Architecture- 06CS81 Hardware Based Speculation Tomasulu algorithm and Reorder Buffer Tomasulu idea: 1. Have reservation stations where register renaming is possible 2. Results are directly
More informationAdvanced Computer Architecture CMSC 611 Homework 3. Due in class Oct 17 th, 2012
Advanced Computer Architecture CMSC 611 Homework 3 Due in class Oct 17 th, 2012 (Show your work to receive partial credit) 1) For the following code snippet list the data dependencies and rewrite the code
More informationChapter 4. The Processor
Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations A simplified
More informationCS/CoE 1541 Mid Term Exam (Fall 2018).
CS/CoE 1541 Mid Term Exam (Fall 2018). Name: Question 1: (6+3+3+4+4=20 points) For this question, refer to the following pipeline architecture. a) Consider the execution of the following code (5 instructions)
More informationOutline Review: Basic Pipeline Scheduling and Loop Unrolling Multiple Issue: Superscalar, VLIW. CPE 631 Session 19 Exploiting ILP with SW Approaches
Session xploiting ILP with SW Approaches lectrical and Computer ngineering University of Alabama in Huntsville Outline Review: Basic Pipeline Scheduling and Loop Unrolling Multiple Issue: Superscalar,
More informationCPSC 313, 04w Term 2 Midterm Exam 2 Solutions
1. (10 marks) Short answers. CPSC 313, 04w Term 2 Midterm Exam 2 Solutions Date: March 11, 2005; Instructor: Mike Feeley 1a. Give an example of one important CISC feature that is normally not part of a
More informationCS152 Computer Architecture and Engineering March 13, 2008 Out of Order Execution and Branch Prediction Assigned March 13 Problem Set #4 Due March 25
CS152 Computer Architecture and Engineering March 13, 2008 Out of Order Execution and Branch Prediction Assigned March 13 Problem Set #4 Due March 25 http://inst.eecs.berkeley.edu/~cs152/sp08 The problem
More informationECE 505 Computer Architecture
ECE 505 Computer Architecture Pipelining 2 Berk Sunar and Thomas Eisenbarth Review 5 stages of RISC IF ID EX MEM WB Ideal speedup of pipelining = Pipeline depth (N) Practically Implementation problems
More informationStatic, multiple-issue (superscaler) pipelines
Static, multiple-issue (superscaler) pipelines Start more than one instruction in the same cycle Instruction Register file EX + MEM + WB PC Instruction Register file EX + MEM + WB 79 A static two-issue
More informationPage 1. Recall from Pipelining Review. Lecture 15: Instruction Level Parallelism and Dynamic Execution
CS252 Graduate Computer Architecture Recall from Pipelining Review Lecture 15: Instruction Level Parallelism and Dynamic Execution March 11, 2002 Prof. David E. Culler Computer Science 252 Spring 2002
More informationAs the amount of ILP to exploit grows, control dependences rapidly become the limiting factor.
Hiroaki Kobayashi // As the amount of ILP to exploit grows, control dependences rapidly become the limiting factor. Branches will arrive up to n times faster in an n-issue processor, and providing an instruction
More informationFour Steps of Speculative Tomasulo cycle 0
HW support for More ILP Hardware Speculative Execution Speculation: allow an instruction to issue that is dependent on branch, without any consequences (including exceptions) if branch is predicted incorrectly
More informationGood luck and have fun!
Midterm Exam October 13, 2014 Name: Problem 1 2 3 4 total Points Exam rules: Time: 90 minutes. Individual test: No team work! Open book, open notes. No electronic devices, except an unprogrammed calculator.
More informationCPE 631 Lecture 11: Instruction Level Parallelism and Its Dynamic Exploitation
Lecture 11: Instruction Level Parallelism and Its Dynamic Exploitation Aleksandar Milenkovic, milenka@ece.uah.edu Electrical and Computer Engineering University of Alabama in Huntsville Outline Instruction
More informationThe Pentium II/III Processor Compiler on a Chip
The Pentium II/III Processor Compiler on a Chip Ronny Ronen Senior Principal Engineer Director of Architecture Research Intel Labs - Haifa Intel Corporation Tel Aviv University January 20, 2004 1 Agenda
More informationEECS 470 Final Project Report
EECS 470 Final Project Report Group No: 11 (Team: Minion) Animesh Jain, Akanksha Jain, Ryan Mammina, Jasjit Singh, Zhuoran Fan Department of Computer Science and Engineering University of Michigan, Ann
More informationCS 2506 Computer Organization II Test 2
Instructions: Print your name in the space provided below. This examination is closed book and closed notes, aside from the permitted one-page formula sheet. No calculators or other computing devices may
More informationTHE HONG KONG UNIVERSITY OF SCIENCE & TECHNOLOGY Computer Organization (COMP 2611) Spring Semester, 2014 Final Examination
THE HONG KONG UNIVERSITY OF SCIENCE & TECHNOLOGY Computer Organization (COMP 2611) Spring Semester, 2014 Final Examination May 23, 2014 Name: Email: Student ID: Lab Section Number: Instructions: 1. This
More informationLoad1 no Load2 no Add1 Y Sub Reg[F2] Reg[F6] Add2 Y Add Reg[F2] Add1 Add3 no Mult1 Y Mul Reg[F2] Reg[F4] Mult2 Y Div Reg[F6] Mult1
Instruction Issue Execute Write result L.D F6, 34(R2) L.D F2, 45(R3) MUL.D F0, F2, F4 SUB.D F8, F2, F6 DIV.D F10, F0, F6 ADD.D F6, F8, F2 Name Busy Op Vj Vk Qj Qk A Load1 no Load2 no Add1 Y Sub Reg[F2]
More informationEXAM #1. CS 2410 Graduate Computer Architecture. Spring 2016, MW 11:00 AM 12:15 PM
EXAM #1 CS 2410 Graduate Computer Architecture Spring 2016, MW 11:00 AM 12:15 PM Directions: This exam is closed book. Put all materials under your desk, including cell phones, smart phones, smart watches,
More informationChapter 3 (CONT II) Instructor: Josep Torrellas CS433. Copyright J. Torrellas 1999,2001,2002,2007,
Chapter 3 (CONT II) Instructor: Josep Torrellas CS433 Copyright J. Torrellas 1999,2001,2002,2007, 2013 1 Hardware-Based Speculation (Section 3.6) In multiple issue processors, stalls due to branches would
More informationInstruction Level Parallelism. Appendix C and Chapter 3, HP5e
Instruction Level Parallelism Appendix C and Chapter 3, HP5e Outline Pipelining, Hazards Branch prediction Static and Dynamic Scheduling Speculation Compiler techniques, VLIW Limits of ILP. Implementation
More informationRecall from Pipelining Review. Lecture 16: Instruction Level Parallelism and Dynamic Execution #1: Ideas to Reduce Stalls
CS252 Graduate Computer Architecture Recall from Pipelining Review Lecture 16: Instruction Level Parallelism and Dynamic Execution #1: March 16, 2001 Prof. David A. Patterson Computer Science 252 Spring
More informationENGR 100 Midterm (CSE Part) Winter 2014
ENGR 100 Midterm (CSE Part) Winter 2014 There are two parts in this midterm. This part focuses on the CSE aspects of the course. You will have 80 minutes to work on the exam. We recommend you spend about
More informationEECS 470. Branches: Address prediction and recovery (And interrupt recovery too.) Lecture 6 Winter 2018
EECS 470 Branches: Address prediction and recovery (And interrupt recovery too.) Lecture 6 Winter 2018 Slides developed in part by Profs. Austin, Brehob, Falsafi, Hill, Hoe, Lipasti, Martin, Roth, Shen,
More informationThis Set. Scheduling and Dynamic Execution Definitions From various parts of Chapter 4. Description of Two Dynamic Scheduling Methods
10 1 Dynamic Scheduling 10 1 This Set Scheduling and Dynamic Execution Definitions From various parts of Chapter 4. Description of Two Dynamic Scheduling Methods Not yet complete. (Material below may repeat
More informationCS433 Midterm. Prof Josep Torrellas. October 16, Time: 1 hour + 15 minutes
CS433 Midterm Prof Josep Torrellas October 16, 2014 Time: 1 hour + 15 minutes Name: Alias: Instructions: 1. This is a closed-book, closed-notes examination. 2. The Exam has 4 Questions. Please budget your
More informationThe Problem with P6. Problem for high performance implementations
CDB. CDB.V he Problem with P6 Martin, Roth, Shen, Smith, Sohi, yson, Vijaykumar, Wenisch Map able + Regfile value R value Head Retire Dispatch op RS 1 2 V1 FU V2 ail Dispatch Problem for high performance
More informationCISC 662 Graduate Computer Architecture Lecture 11 - Hardware Speculation Branch Predictions
CISC 662 Graduate Computer Architecture Lecture 11 - Hardware Speculation Branch Predictions Michela Taufer http://www.cis.udel.edu/~taufer/teaching/cis6627 Powerpoint Lecture Notes from John Hennessy
More informationChapter 4. The Processor
Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations A simplified
More informationHardware-Based Speculation
Hardware-Based Speculation Execute instructions along predicted execution paths but only commit the results if prediction was correct Instruction commit: allowing an instruction to update the register
More informationELEC 5200/6200 Computer Architecture and Design Fall 2016 Lecture 9: Instruction Level Parallelism
ELEC 5200/6200 Computer Architecture and Design Fall 2016 Lecture 9: Instruction Level Parallelism Ujjwal Guin, Assistant Professor Department of Electrical and Computer Engineering Auburn University,
More informationCOMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface. 5 th. Edition. Chapter 4. The Processor
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle
More informationEECS 270 Midterm Exam
EECS 270 Midterm Exam Fall 2009 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: NOTES: Problem # Points 1 /11 2 /4
More informationChapter 4 The Processor 1. Chapter 4D. The Processor
Chapter 4 The Processor 1 Chapter 4D The Processor Chapter 4 The Processor 2 Instruction-Level Parallelism (ILP) Pipelining: executing multiple instructions in parallel To increase ILP Deeper pipeline
More informationSuper Scalar. Kalyan Basu March 21,
Super Scalar Kalyan Basu basu@cse.uta.edu March 21, 2007 1 Super scalar Pipelines A pipeline that can complete more than 1 instruction per cycle is called a super scalar pipeline. We know how to build
More informationComplex Pipelining COE 501. Computer Architecture Prof. Muhamed Mudawar
Complex Pipelining COE 501 Computer Architecture Prof. Muhamed Mudawar Computer Engineering Department King Fahd University of Petroleum and Minerals Presentation Outline Diversified Pipeline Detecting
More informationCMSC Computer Architecture Lecture 18: Exam 2 Review Session. Prof. Yanjing Li University of Chicago
CMSC 22200 Computer Architecture Lecture 18: Exam 2 Review Session Prof. Yanjing Li University of Chicago Administrative Stuff! Lab 5 (multi-core) " Due: 11:59pm, Dec. 1 st, Thursday " Two late days with
More informationCMSC411 Fall 2013 Midterm 2 Solutions
CMSC411 Fall 2013 Midterm 2 Solutions 1. (12 pts) Memory hierarchy a. (6 pts) Suppose we have a virtual memory of size 64 GB, or 2 36 bytes, where pages are 16 KB (2 14 bytes) each, and the machine has
More informationCS 2506 Computer Organization II Test 2. Do not start the test until instructed to do so! printed
Instructions: Print your name in the space provided below. This examination is closed book and closed notes, aside from the permitted fact sheet, with a restriction: 1) one 8.5x11 sheet, both sides, handwritten
More informationComputer Architecture 计算机体系结构. Lecture 4. Instruction-Level Parallelism II 第四讲 指令级并行 II. Chao Li, PhD. 李超博士
Computer Architecture 计算机体系结构 Lecture 4. Instruction-Level Parallelism II 第四讲 指令级并行 II Chao Li, PhD. 李超博士 SJTU-SE346, Spring 2018 Review Hazards (data/name/control) RAW, WAR, WAW hazards Different types
More informationEE382A Lecture 7: Dynamic Scheduling. Department of Electrical Engineering Stanford University
EE382A Lecture 7: Dynamic Scheduling Department of Electrical Engineering Stanford University http://eeclass.stanford.edu/ee382a Lecture 7-1 Announcements Project proposal due on Wed 10/14 2-3 pages submitted
More informationThis Set. Scheduling and Dynamic Execution Definitions From various parts of Chapter 4. Description of Three Dynamic Scheduling Methods
10-1 Dynamic Scheduling 10-1 This Set Scheduling and Dynamic Execution Definitions From various parts of Chapter 4. Description of Three Dynamic Scheduling Methods Not yet complete. (Material below may
More informationInstruction Pipelining Review
Instruction Pipelining Review Instruction pipelining is CPU implementation technique where multiple operations on a number of instructions are overlapped. An instruction execution pipeline involves a number
More informationLECTURE 3: THE PROCESSOR
LECTURE 3: THE PROCESSOR Abridged version of Patterson & Hennessy (2013):Ch.4 Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU
More informationQuestion 1: (20 points) For this question, refer to the following pipeline architecture.
This is the Mid Term exam given in Fall 2018. Note that Question 2(a) was a homework problem this term (was not a homework problem in Fall 2018). Also, Questions 6, 7 and half of 5 are from Chapter 5,
More informationComputer Architecture Lecture 13: State Maintenance and Recovery. Prof. Onur Mutlu Carnegie Mellon University Spring 2013, 2/15/2013
18-447 Computer Architecture Lecture 13: State Maintenance and Recovery Prof. Onur Mutlu Carnegie Mellon University Spring 2013, 2/15/2013 Reminder: Homework 3 Homework 3 Due Feb 25 REP MOVS in Microprogrammed
More informationCOMPUTER ORGANIZATION AND DESIGN
COMPUTER ORGANIZATION AND DESIGN 5 Edition th The Hardware/Software Interface Chapter 4 The Processor 4.1 Introduction Introduction CPU performance factors Instruction count CPI and Cycle time Determined
More informationEECS Digital Design
EECS 150 -- Digital Design Lecture 11-- Processor Pipelining 2010-2-23 John Wawrzynek Today s lecture by John Lazzaro www-inst.eecs.berkeley.edu/~cs150 1 Today: Pipelining How to apply the performance
More informationQuestion 1 (5 points) Consider a cache with the following specifications Address space is 1024 words. The memory is word addressable The size of the
Question 1 (5 points) Consider a cache with the following specifications Address space is 1024 words. he memory is word addressable he size of the cache is 8 blocks; each block is 4 words (32 words cache).
More informationInstruction Level Parallelism
Instruction Level Parallelism The potential overlap among instruction execution is called Instruction Level Parallelism (ILP) since instructions can be executed in parallel. There are mainly two approaches
More informationEECS 373 Midterm Winter 2012
EECS 373 Midterm Winter 2012 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Nor did I discuss this exam with anyone after
More informationEE557--FALL 2001 MIDTERM 2. Open books
NAME: SOLUTIONS STUDENT NUMBER: EE557--FALL 2001 MIDTERM 2 Open books Q1: /16 Q2: /12 Q3: /8 Q4: /8 Q5: /8 Q6: /8 TOTAL: /60 Grade: /25 1 QUESTION 1(Tomasulo with ROB) 16 points Consider the following
More informationFinal Exam Fall 2007
ICS 233 - Computer Architecture & Assembly Language Final Exam Fall 2007 Wednesday, January 23, 2007 7:30 am 10:00 am Computer Engineering Department College of Computer Sciences & Engineering King Fahd
More informationHardware-Based Speculation
Hardware-Based Speculation Execute instructions along predicted execution paths but only commit the results if prediction was correct Instruction commit: allowing an instruction to update the register
More informationFloating Point/Multicycle Pipelining in DLX
Floating Point/Multicycle Pipelining in DLX Completion of DLX EX stage floating point arithmetic operations in one or two cycles is impractical since it requires: A much longer CPU clock cycle, and/or
More informationארכי טק טורת יחיד ת עיבוד מרכזי ת
ארכי טק טורת יחיד ת עיבוד מרכזי ת (36113741) תשס"ג סמסטר א' March, 2007 Hugo Guterman (hugo@ee.bgu.ac.il) Web site: http://www.ee.bgu.ac.il/~cpuarch Arch. CPU L5 Pipeline II 1 Outline More pipelining Control
More informationCIS 662: Midterm. 16 cycles, 6 stalls
CIS 662: Midterm Name: Points: /100 First read all the questions carefully and note how many points each question carries and how difficult it is. You have 1 hour 15 minutes. Plan your time accordingly.
More informationEECS 570 Final Exam - SOLUTIONS Winter 2015
EECS 570 Final Exam - SOLUTIONS Winter 2015 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: # Points 1 / 21 2 / 32
More informationEPC6055 Digital Integrated Circuits EXAM 1 Fall Semester 2013
EPC6055 Digital Integrated Circuits EXAM 1 Fall Semester 2013 Print Here Student ID Signature This is a closed book exam. The exam is to be completed in one-hundred ten (110) minutes. Don t use scratch
More informationEITF20: Computer Architecture Part3.2.1: Pipeline - 3
EITF20: Computer Architecture Part3.2.1: Pipeline - 3 Liang Liu liang.liu@eit.lth.se 1 Outline Reiteration Dynamic scheduling - Tomasulo Superscalar, VLIW Speculation ILP limitations What we have done
More informationQ1: Finite State Machine (8 points)
Q1: Finite State Machine (8 points) Answer the questions below for the finite state machine in this diagram: 1. Complete the truth table shown below. (2 points) Input Output State In State Out S 0 = 00
More informationCS 152 Computer Architecture and Engineering
CS 152 Computer Architecture and Engineering Lecture 7 Pipelining I 2005-9-20 John Lazzaro (www.cs.berkeley.edu/~lazzaro) TAs: David Marquardt and Udam Saini www-inst.eecs.berkeley.edu/~cs152/ Office Hours
More informationCS152 Computer Architecture and Engineering. Complex Pipelines
CS152 Computer Architecture and Engineering Complex Pipelines Assigned March 6 Problem Set #3 Due March 20 http://inst.eecs.berkeley.edu/~cs152/sp12 The problem sets are intended to help you learn the
More informationLast lecture. Some misc. stuff An older real processor Class review/overview.
Last lecture Some misc. stuff An older real processor Class review/overview. HW5 Misc. Status issues Answers posted Returned on Wednesday (next week) Project presentation signup at http://tinyurl.com/470w14talks
More information