ENGR 100 Midterm (CSE Part) Winter 2014

Transcription

1 ENGR 100 Midterm (CSE Part) Winter 2014 There are two parts in this midterm. This part focuses on the CSE aspects of the course. You will have 80 minutes to work on the exam. We recommend you spend about 55 minutes on the CSE part and 25 minutes on the TC part. The exam is closed book. You are to abide by the University of Michigan Engineering honor code. Please sign below to indicate that you have abided by the honor code on this exam. Honor code pledge: I have neither given nor received unauthorized aid on this examination, nor have I concealed any violations of the Honor Code. Signature: Name: Uniqname: Problem 1 out of 20 Problem 2a out of 14 Problem 2b out of 9 Problem 2c out of 27 Total out of 70 Page 1 of 9

2 1 Successive approximation [20 percent] You are given a circuit module square root that, given a number N and an approximation to N, computes a closer approximation of N. Here are the interfaces to the square root module and other standard modules: module square_root( input wire [13:0] N, input wire [7:0] approximation, output reg [7:0] closer_approximation); // code omitted for brevity module tristate( input wire [7:0] in, output reg [7:0] out, input wire drive); // code omitted for brevity module register( input wire clock, input wire reset, input wire write, input wire [7:0] data_in, output reg [7:0] data_out); // code omitted for brevity module memory( input wire clock, input wire [7:0] address, input wire address_write, input wire [7:0] data_in, input wire memory_write, output wire [7:0] data_out); // code omitted for brevity Your job is to build a digital circuit that uses these modules (you may not need all of them) to compute the value of N via successive approximation. Successive approximation computes a closer and closer answer by refining the answer over several iterations. On each clock cycle, your circuit should produce a closer approximation to N. N is an input into your circuit. Use KEY[0] as the reset signal, and use KEY[1] as the clock. Display the answer on LED RED[7:0]. 1a. What important engineering concept allows you to use the square root module in your circuit without knowing how square root is implemented? Page 2 of 9

3 1b. Draw the top module of your circuit as a schematic. Label all inputs and outputs from each module you use with the names given in the module. 1c. Write the top module of your circuit in Verilog. module top( input wire [3:0] KEY, input wire [13:0] N, output [7:0] LED_RED); Page 3 of 9

4 2 Fibonacci sequence A parameterized Fibonacci sequence is a sequence of numbers, in which each element is the sum of the previous two elements, except for the first two elements (which are defined according to parameters element 0 and element 1 ). You are probably familiar with the Fibonacci sequence with element 0 = 0 and element 1 = 1: 0, 1, 1, 2, 3, 5, 8, 13, 21,.... Implement a digital circuit that computes the first 32 elements of a parameterized Fibonacci sequence and stores them in memory (addresses 0-31). element 0 and element 1 are input as wires to the circuit. For example, here are the desired memory contents for a Fibonacci sequence with element 0 = 2 and element 1 = 5. address value Page 4 of 9

5 2a Datapath [14 percent] Draw the datapath for this circuit. Draw registers and memory as rectangles, tri-state drivers as triangles, and other combinational logic as circles. Show all wires (or groups of wires) that connect datapath elements. Name all signals that you will need to refer to in the control unit. Remember to show how the input and output signals are connected in the datapath. Include only those elements and wires that are needed to implement the algorithm. You need not show the control unit, clock, or reset on this datapath. Page 5 of 9

6 2b Combinational logic blocks [9 percent] Write the Verilog code for each unique combinational logic block used in your datapath (not including tri-state drivers). You need only show the blocks; i.e. you need not show module or variable declarations. Page 6 of 9

7 2c Control unit [27 percent] Write the control unit for this circuit by filling in the truth table on the following pages (you need not use all rows or columns shown). Use blanks in the cells for control signals to indicate a value of zero. Use blanks in the cells for input signals to indicate that their value is ignored. Describe the actions of each row in the Comment column (use pseudo-code). Page 7 of 9

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