Vertical Reuse of functional verification from subsystem to SoC level (with seamless SoC emulation)

Transcription

1 Vertical Reuse of functional verification from subsystem to SoC level (with seamless SoC emulation) Pranav Kumar, Staff Engineer Digvijaya Pratap SINGH, Sr. Staff Engineer STMicroelectronics, Greater NOIDA, INDIA Ankur Jain, Verification Technologist Mentor Graphics, Bangalore, INDIA Accellera Systems Initiative 1

2 Introduction Ever increasing SoC complexity Verification challenge Two levels of verification IP/Subsystem Level SoC Level (integration aspects) Full application scenarios FPGA prototyping Emulation Verification methodology standardization UVM Accellera Systems Initiative 2

3 Typical verification Environments Tests Clock/Re set control Subsystem Level Central Control / CPU Model Bus Functio nal model Interrup t controll er Bus IF IP/ Subsystem VIP Top Clock/Reset VIC DMA RAM ROM SoC IP1 IP2 IP3 VIP1 VIP2 VIP3 SoC Level C-Tests CPU IP4 VIP4 Accellera Systems Initiative 3

4 Standardizing subsystem level verification Env Tests Clock/Re set control Central Control / CPU Model Bus Functio nal model Interrup t controll er Bus IF IP/ Subsystem VIP LVP Top Clock/Reset VIC DMA RAM SoC IP1 IP2 VIP1 VIP2 ROM IP3 VIP3 C-Tests CPU IP4 VIP4 Accellera Systems Initiative 4

5 LVP Lightweight Virtual Platform Processer subsystem in SystemC/TLM TLM ARM ISS Abstracted TLM interconnect C++ Memory models integrated in SystemC VIC and DMAC TLM models Bus interface bridges AMBA and STBus Accellera Systems Initiative 5

6 Emulation Env CPU (e.g. ARM RTL or ISS model) Interconnect DUT (e.g. PCIe End-point) VAL Apps code incl DUT driver layer Instrument or real device (isolve PCIe or PC) External interface now driven by real hardware or external device models Addressing the simulation speed bottleneck Useful for concurrent/full application verification scenarios Early software development, e.g. boot rom code, etc. Accellera Systems Initiative 6

7 Reuse simulation to emulation Accellera Systems Initiative 7

8 Reuse major challenges Easy portability of VIP Consider VIP as another IP with Custom registers set VIP driver in C Standard bus interface C & SV/UVM Synchronization VIP env in SV/UVM VIP driver in C solution Develop custom VIPs OR Interface VIPs with intermediary layer mentioned here as VAL (Verification Abstraction Layer) Accellera Systems Initiative 8

9 VAL Central Idea Control on complete verification environment VIP reset and config IP config VIP and IP activities synchronization Allow SW-driven constrained test randomization Configuration parameters Data Control score-boarding Enable / disable Reference data and configuration values transfer Initiate backdoor operations Accesses to LVP and VIP memories Accellera Systems Initiative 9

10 VAL - Implementation A generic configurable component with two sub-layers: a) VAL_FE (VAL FrontEnd) Interface to any standard (AMBA, STBus, etc.) bus, or proprietary bus or TLM model b) The VAL_BE (VAL BackEnd) Interface between VAL_FE and VIP converts instructions from VAL_FE to configuration or data packets and sequence generation or control of existing sequences Accellera Systems Initiative 10

11 VAL In verification environment Accellera Systems Initiative 11

12 seqs Understanding VAL flow 1. VAL trigger from C 2. Cfg randomization (constrained,.) 3. Cfg updated in Memory model 4. C test reads Cfg information from Memory 5. C test programs Subsystem/IP in according configurations Val Flow - Steps. valtrig();. Driver VAL BE Monitor Sequencer C SubSys. (RTL) Accellera Systems Initiative 12

13 Testbench Architecture LVP (Lightweight Virtual Platform) A processer subsystem (SystemC/TLM) with multiple AMBA interfaces to control the DUT & VIP. VAL (Verification Abstraction Layer) C to SV/UVM interface Provides control, triggering and synchronization of UVM VIP - configuration, randomization and sequences from a C testcase running on the LVP. Provides control of other testbench components e.g. scoreboard. TLM ports to trigger and synchronize VIP Connected to LVP through VAL via AMBA interface Where AMBA i/f can be replaced with any other bus i/f Providing APIs for controlling QVIP configuration and sequences Triggering above QVIP APIs from C, and synchronizing using TLM Accellera Systems Initiative 13

14 Testframe.sv Example Testbench Lightweight Virtual Platform (LVP) AXI Master AXI Master T3 Slave Interrupts Clock Reset A S Y N A S Y N C A S Y N C C APB N o d e C o n v A MMU A APB C o n v APBto Micro SS Reg Master Cfg Regs Controller Core PCS PHY Memory DUT xtal AHB S VAL Score Board Active RC/EP PCIe VIP Passive EP/RC Accellera Systems Initiative 14

15 VIP as an IP Identify configuration parameters of the VIP Define C data-structure for them custom registers set Develop VIP driver using above data structures configuration/control functions read/write transactions functions Interrupt handlers Accellera Systems Initiative 15

16 Example: VIP registers description in C typedef union { struct { uint32_t tlp_type : 8; // [7:0] uint32_t reserved : 7; // [14:8] uint32_t bar_size : 1; // [15] uint32_t unused_0 : 16; // [31:16] } BitI; uint32_t RegI; } t_pcie_qvip_tlp_id_reg; typedef union { struct { uint32_t seq_id : 32; // [31:0] } BitI; uint32_t RegI; } t_pcie_qvip_seq_id_reg;. The Verification component configuration has been arranged in register set and made word addressable C declaration for registers typedef struct { #ifdef BLOCK_LEVEL uint32_t* VAL_TRIG; #else uint32_t VAL_TRIG; #endif The register set for Verification IP are mapped to consecutive addresses in memory, reserving 0th for VAL triggers. t_pcie_qvip_seq_id_reg PCIe_QVIP_SEQ_ID_REG; t_pcie_qvip_seq_addrl_reg PCIe_QVIP_SEQ_ADDRL_REG; t_pcie_qvip_seq_addrh_reg PCIe_QVIP_SEQ_ADDRH_REG; t_pcie_qvip_seq_data_len_reg PCIe_QVIP_SEQ_DATA_LEN_REG; t_pcie_qvip_seq_data_ref_reg PCIe_QVIP_SEQ_DATA_REF_REG; t_pcie_qvip_plp_reg PCIe_QVIP_PLP_REG; t_pcie_qvip_end_seq_reg PCIe_QVIP_END_SEQ_REG; t_pcie_qvip_sync_flag PCIe_QVIP_SYNC_FLAG; t_pcie_qvip_msi_off PCIe_QVIP_MSI_OFF; t_pcie_qvip_dllp_reg PCIe_QVIP_DLLP_REG; } PCIe_QVIP_registers; Accellera Systems Initiative 16

17 C & SV/UVM Synchronization Synchronization needed so that VIP and IP are configured before test is initiated (SV env) VIP s sequencer should wait and not flow-in Blocking port used to block sequencer VIP configuration based on SV/UVM config classes VAL provides trigger for the configuration Sequences to be run on the VIP sequencer also controlled from VAL Accellera Systems Initiative 17

18 Example - Synchronization typedef struct { uint32_t* VAL_TRIG; t_pcie_qvip_seq_id_reg PCIe_QVIP_SEQ_ID_REG; t_pcie_qvip_seq_addrl_reg PCIe_QVIP_SEQ_ADDRL_REG; t_pcie_qvip_dllp_reg PCIe_QVIP_DLLP_REG; } PCIe_QVIP_registers; void PCIe_QVIP_init(PCIe_QVIP_desc* p, uint32_t base_addr) { PCIe_QVIP_REGMAP = (PCIe_QVIP_registers*) base_addr; #ifdef BLOCK_LEVEL PCIe_QVIP_REGMAP->VAL_TRIG = (uint32_t*) PCIE_QVIP_START; #endif } C header for VIP [TRIG] Trigger from C to unblock Sequencer: class pcie_qvip_sequencer extends uvm_sequencer; `uvm_sequencer_utils(pcie_qvip_sequencer) uvm_blocking_get_port #(pcie_qvip_data) val_port;. mvc_sequencer pcie_vip_sqr; function new (string name = "pcie sequencer",.); super.new(name,parent); val_port = new("val_port", this); endfunction: new endclass: pcie_qvip_sequencer Called from sequence to un-block Blocking port to stop VIP Sequence: virtual task body(); forever begin p_sequencer.val_port.get(d);.. endtask: body Accellera Systems Initiative 18

19 Example - Configuration and Data Flow Control via VAL V A L E N V QVIP VAL BE Mem_data TEST VAL BE Config Data ana_exp Seq FIFO Uvm_blocking_get_port Test_config Test_data Cfg_port Uvm_analysis_imp get_exp Coverage SCOREBOARD end_seq_port Uvm_analysis_port Write Fn Uvm_blocking_get_port val_port SEQUENCER Seq_data_port Uvm_analysis_port Uvm_analysis_port VIP ENV DRIVER MONITOR Accellera Systems Initiative 19

20 Configuration and Data Flow Control Two VAL_BE interfaces a) QVIP_VAL_BE Two ports i. Config ii. via VAL (cont ) configuration/control packets Data data transactions along with required control of sequence b) TEST_VAL_BE Two ports i. test_config randomization of the test/config parameters transfer to main memory and coverage-collector ii. test_data providing reference and test data to scoreboard Accellera Systems Initiative 20

21 S/W Framework layers for Reuse Test impl. SS level To SoC level SoC APIs For clock/reset SoC APIs for IP/Subsystem level signals control and status Call Test*() Test definition layer Low Level Drivers for subsystem, interrupt handlers, etc. Low Level Driver (API) SS Header SS SS cmp Header Header SS Files Files Header Files Files Interrupt Handler (API) HAL (Hardware Abstraction Layer) operating directly on IP Registers IP-Xact Description of IP Accellera Systems Initiative 21

22 Conclusion Testplan and coverage shared with SoC team Reused for SoC verification plan. Subsystem LLD, Testcases successfully re-used from sub-system level to SoC level Re-used further in emulation (thanks to VAL) Subsystem LLD re-used for silicon validation Accellera Systems Initiative 22

23 Questions Accellera Systems Initiative 23