ARM s IP and OSCI TLM 2.0

Transcription

1 ARM s IP and OSCI TLM 2.0 Deploying Implementations of IP at the Programmer s View abstraction level via RealView System Generator ESL Marketing and Engineering System Design Division ARM Q108 1

2 Contents OSCI TLM 2.0 Experiences with implementing draft 1, use cases, draft 2, Suggestions for improvement AMBA PV Defining AXI, AHB and APB at the PV level System Generator and Model Export Deploying ARM IP PV models into the environment Ports, Scheduling, Debug Interface Availability of ARM IP PV Models 2

3 The Big Picture Membership of OSCI board. Active participation in the TLM Working Group. ARM s view of OSCI TLM 2.0 Becoming industry standard at the interface Deployment of IP to multiple development platforms Unexposed sub-system interfaces not necessarily TLM 2.0 Freedom to define higher performance interfaces PV/UT only Lack of semantic checks, e.g. communication protocols No assistance for defining target debug ARM s Use Cases for TLM 2.0 Software Development (2.1*) App, OS,...Driver... Software Performance Analysis (2.2)...dependent on definition of reasonable! (2.4), (2.7) are considered by ARM to be at the CA level That said... * Numbers refer to requirements in TLM 2.0 draft 2 requirements doc 3

4 TLM 2.0 draft 1 -> draft 2 Single Transaction object REQ and RESP combined in Generic Payload Simulation speed improvement At PV Level, separate REQ and RESP not used anyway simplest (quickest) mechanism for (2.1) b_transport only (Could add timing notion - see later) Extension mechanism improved Dynamic casting no longer necessary for performance as per draft 1 Support of DMI e.g. Memory in System C without huge simulation speed hit Quantum Keeper Possibly formalises ARM s approach Documentation significantly improved 4

5 TLM 2.0 Final Improvements (1) DMI Current DMI proposal is not suitable for AXI in its entirety For example, S / NS memories at the same address Secure Secure Memory Interconnect Non-secure Nonsecure Memory Same problem with debug accesses Carry the same type as normal transactions (GP)? 5

6 TLM 2.0 Final Improvements (2) Specific Protocol Would like to use inheritance Not recommended by draft2 Rules out - Extended Compile time checks For example between different versions of protocols Rules out - Refining behaviours of the GP Rules out Adding extension specific helper function Synchronization Early Termination of quantum with Synchronize now command to all the platform Status flag in b_transport call requesting that an initiator terminates its quantum early? (Possibly related to adding time to b interface) Would improve simulation efficiency, 6

7 TLM 2.0 Final Improvements (3) Abstraction Levels Blocking / Non-Blocking. UT/LT/AT, PV/PV+T Confusion Can have timing at UT level (UT means no timing at the interface) Seeking to simplify... Suggestion: Extend blocking interface to carry a time stamp Remove/Rename UT? What does this mean for LT? (LLT?) Enhances Symmetry Path Identification No standard means to discriminate/distinguish between several incoming paths Example: dual-port memory with arbitration based on incoming path Example: Effects of arbitration schemes in cross bar switch 7

8 AMBA PV Implementation of AXI, AHB, APB on top of TLM 2.0 Currently based on draft 1, migration to draft 2 in progress Free download (not yet) Example of how to bridge protocols Can be used to as an example of how to construct other bridges Blocking Interface wait() can be called by the transaction target Signal API part of the AMBA PV package even though it s not AXI Dynamic Casting Avoided in AMBA PV by using inheritance Transport of, e.g. (REQ, EXT) tlm_custom_base -> (AMBA_PV_REQ) Converting AMBA PV to amba_pv_control TLM 2.0 is (almost) cost free tlm_request amba_pv_request 8

9 System Generator System Generator Preferred modeling/ip proliferation environment Model debug support, ease of use, graphical visualization Highest simulation speed for PV ~ 250 MIPS Model Export TLM 2.0 draft 1 examples delivered today, draft 2 in preparation First tool to support TLM 2.0 Simulation speed largely maintained 9

10 Model Export - Interfaces Interface generation for mixed system consisting of ARM PV models and OSCI TLM 2.0 draft 1 compliant components ARM sub-system OSCI - TLM 2.0 draft 1 Components Top Level System MEM Slave SystemC Master DMA CPU Master External Ports MEM SystemC Slave Generated Port Wrapper 10

11 Model Export Scheduling System Generator Virtual Platform SystemC Components Master Scheduler (generated from SG) control control System Generator Scheduler System Generator Components Data SystemC Components SystemC Scheduler Master Scheduler Synchronization of simulated time for System Generator and SystemC domain Local Schedulers Schedule components within their domain 11

12 Simulation Control Simulation Control API Clock Clock ratio between SG and SysC worlds Divergent local clocks Ordering not absolute time is critical Set Quantum Controls Synchronization between two subsystems. Currently fixed Managed to ensure Interrupts are taken (Hard) Real Time constraints Driver Development Performance vs. accuracy (again) Stop Simulation DEBUG MODE starts debug server Model Configuration/Parameterization API Get/Set parameters in SG components Load Software Files for Processors 12

13 Model Export - Debugging System Generator Virtual Platforms Fully supported by Model Debugger and RVD Attach to running simulations run, cycle, set breakpoints source-level debugging etc. System Generator Virtual Platform SystemC Components Model Debugger / RVD CADI Debug Client CADI Debug Server Top Level System MEM CPU Slave Master SystemC Master DMA MEM SystemC Slave built in debug support handwritten debug support 13

14 ARM IP PV Model Availability ARM CPU models ARM926EJ ARM968E ARM1136J ARM1176JZ Cortex-A8 Cortex-R4 Roadmap Cortex-A9 ARM11MPCore Pre-built models CP Baseboard Emulation Baseboard DualCore Platform Bus interfacing (PV-bus is the model interconnect; represents the functionality of PL300, PL301) ARM fabric peripheral models UART PL011 Timers SP804 Clocks PL030, PL031, ICS307 GPIO PL061 Generic Interrupt Controller PL390 Vectored Interrupt Controller PL192 TrustZone Interrupt Controller SP890 Memory models RAM Flash NAND-Flash Controllers DMAC PL080, DMC PL340, SMC PL350 TZMA BP141, TZPC BP147 Complex peripheral models CLCD controller PL110, PL111 Ethernet controller ( LAN91C111 ) 14