Multi-cycle Approach. Single cycle CPU. Multi-cycle CPU. Requires state elements to hold intermediate values. one clock cycle or instruction
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1 Multi-cycle Approach Single cycle CPU State element Combinational logic State element clock one clock cycle or instruction Multi-cycle CPU Requires state elements to hold intermediate values State Element A Combinational logic State Element B State Element N- Combinational logic State Element N clock one clock cycle one instruction
2 Multi-cycle Approach Each cycle must Store values needed in a later cycle of the current instruction in an internal register. All except IR hold data for one clock cycle. PC Memory Address Data (Instr. or Data) IR MDR Addr Register Data Addr File Write Addr Data A B Out IR Instruction Register MDR Memory Data Register A, B Register File data Out Result Register Store values needed by subsequent instructions in the register file or memory
3 Multi-cycle Control New control signals needed PCWriteCond is set during a beq instruction Formerly called Branch signal PCWrite is set to write PC Unconditional write signal needed during Fetch cycle IorD controls what address is used for the memory PC holds address for fetch cycle Out holds address for memory access instructions IRWrite controls when the IR is written SrcA control one input to rs register for most operations PC for branch instructions Old Src renamed SrcB and expanded 3
4 Multi-cycle Control and Datapath PCWriteCond PCWrite IorD Mem MemWrite MemtoReg IRWrite PCSource Op Control SrcB SrcA RegWrite RegDst Instr [3-6] PC[3-8] Instr[5-] left 8 PC Address Memory Data (Instr. or Data) IR MDR Instr[5-] Addr Addr Write Addr Register File Sign Extend 3 Data Data left A B Instr[5-] zero control Out
5 Multi-cycle Steps Instruction Fetch Decode and Register Fetch Execution Memory Access Write Register File 5
6 () Instruction Fetch Cycle Increment PC using PC = PC + 4 instruction from memory IR = M[PC] Control signals must Select memory address source Enable memory reading Enable PC and IR write Select PC source Select input as PC and constant 4 Select operation (addition) 6
7 Instruction Fetch PCWriteCond PCWrite IorD Mem MemWrite MemtoReg IRWrite PCSource Op Control SrcB SrcA RegWrite RegDst Instr [3-6] PC[3-8] Instr[5-] left 8 PC Address Memory Data (Instr. or Data) IR MDR Instr[5-] Addr Addr Write Addr Register File Sign Extend 3 Data Data left A B Instr[5-] zero control Out
8 () Decode and Register Fetch Cycle register values A = R[rs], B = R[rt] Compute branch destination Out = PC + sign extended immediate value Prepare for next step based on instruction Control signals must Select inputs as PC and immediate value Select operation (addition) 8
9 Decode and Register Fetch PCWriteCond PCWrite IorD Mem MemWrite MemtoReg IRWrite PCSource Op Control SrcB SrcA RegWrite RegDst Instr [3-6] PC[3-8] Instr[5-] left 8 PC Address Memory Data (Instr. or Data) IR MDR Instr[5-] Addr Addr Write Addr Register File Sign Extend 3 Data Data left A B Instr[5-] zero control Out
10 (3) Execution Cycle Functionality varies with instructions Memory reference Compute address Out = A + sign extended immediate R-type Compute operation Out = A op B Branch Store new PC if needed PC = Out Out contains branch destination from previous cycle Control signals will depend on instruction type Mem/R-type: Select input and operation Branch: Select PC source and set PC write control signal if needed
11 Execute Branch PCWriteCond PCWrite IorD Mem MemWrite MemtoReg IRWrite PCSource Op Control SrcB SrcA RegWrite RegDst Instr [3-6] PC[3-8] Instr[5-] left 8 PC Address Memory Data (Instr. or Data) IR MDR Instr[5-] Addr Addr Write Addr Register File Sign Extend 3 Data Data left A B 4 3 Instr[5-] zero control Out
12 (4) Memory Access Cycle Functionality varies with instructions Memory reference memory (lw) or write memory (sw) MDR = M[Out] or M[Out] = B R-type Write result to register file R[rd] = Out Control signals will depend on instruction type Memory reference Enable memory read or write Select memory address R-type Select register file write address and data Enable register file write
13 R-Type Memory Access PCWriteCond PCWrite IorD Mem MemWrite MemtoReg IRWrite PCSource Op Control SrcB SrcA RegWrite RegDst Instr [3-6] PC[3-8] Instr[5-] left 8 PC Address Memory Data (Instr. or Data) IR MDR Instr[5-] Addr Addr Write Addr Register File Sign Extend 3 Data Data left A B Instr[5-] zero control Out
14 (5) Write Register File Cycle Only used by load instructions Write memory value to register Reg[rt] = MDR Control signals must Enable register file write Select register file write address and data 4
15 lw Write Registers PCWriteCond PCWrite IorD Mem MemWrite MemtoReg IRWrite PCSource Op Control SrcB SrcA RegWrite RegDst Instr [3-6] PC[3-8] Instr[5-] left 8 PC Address Memory Data (Instr. or Data) IR MDR Instr[5-] Addr Addr Write Addr Register File Sign Extend 3 Data Data left A B Instr[5-] zero control Out
16 Review PCWriteCond PCWrite IorD Mem MemWrite MemtoReg IRWrite PCSource Op Control SrcB SrcA RegWrite RegDst Instr [3-6] PC[3-8] Instr[5-] left 8 PC Address Memory Data (Instr. or Data) IR MDR Instr[5-] Addr Addr Write Addr Register File Sign Extend 3 Data Data left A B Instr[5-] zero control out
17 Defining the CPU Control Use a finite state machine model to design the control Control now has state or memory Action depends on input and current cycle Signal names in each state are asserted Asserted signals are set or enabled Unlisted signals are deasserted Arcs between states list conditions for transition A Example State A Signal Run is asserted Goes to State B when input Up = Goes to State C when input Up = Up= B Run Up= C 7
18 Instruction Fetch and Decode Cycles Start Mem IorD IRWrite SrcA SrcB Op PCSource PCWrite Fetch Instruction Increment PC Mem IorD = IRWrite SrcA = SrcB = Op = PCSource = PCWrite Instruction Fetch SrcA SrcB Op SrcA = SrcB = Op = Decode Next state depends on instruction 8 Compute Branch Destination
19 Memory Access Instructions From Decode state if SW or LW SrcA = SrcB = Op = Execute Cycle - Compute memory address LW Mem IorD = SW MemWrite IorD = Memory Access Cycle - or write memory RegWrite MemtoReg = RegDst = Fetch Next Instruction Write Register File Cycle - Load instruction only 9
20 R-type Instructions From Decode state if R-type SrcA = SrcB = Op = Execute Cycle - Compute operation - Control must look at function field RegWrite MemtoReg = RegDst = Memory Access Cycle - Write data to register file Fetch Next Instruction
21 Branch on Equal Instruction From Decode state if BEQ SrcA = SrcB = Op = PCSource = PCWriteCond Execute Cycle - Compare register values - Write PC if Zero asserted Fetch Next Instruction
22 Final State Diagram
23 Implementing jal Jump and link (jal) J-Type PC+4 $3 Jump destination PC What modifications are required? Cycle Const 3 write destination Expand PCSource mux with Out as PC+4 3 Cycle Const 3 write destination PC connected to write data 3
24 Implementing jal what must be done? PCWriteCond PCWrite IorD Mem MemWrite MemtoReg IRWrite PCSource Op Control SrcB SrcA RegWrite RegDst Instr [3-6] PC[3-8] Instr[5-] left 8 PC Address Memory Data (Instr. or Data) IR MDR Instr[5-] Addr Addr Write Addr Register File Sign Extend 3 Data Data left A B Instr[5-] zero control out
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