Topics. FPGA Design EECE 277. Number Representation and Adders. Class Exercise. Laboratory Assignment #2

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1 FPGA Deign EECE 277 Number Repreentation and Adder Dr. William H. Robinon Februar 2, 25 Topi There are kind of people in the world, thoe that undertand binar and thoe that don't. Unknown Adminitrative tuff Laborator Aignment #2 (due Monda, Februar 28) PLEASE do the tutorial in Appendi B, C, and D of the tetbook Number tem Adder iruit 2 Laborator Aignment #2 Quartu II Software Refer to Appendie A, B, C, and D UP2 Deign Laborator Kit Cable Problem #5 Laborator Report Follow guideline from handout Cla Eerie 2 = D = = 27 DEF 6 = = 2 In-Cla Lab Seion Wedneda, Februar 23, 9am am 3 4

2 Poitional Number Repreentation Number in Different Stem Deimal Headeimal Otal Binar Fundamental of Digital Logi: Chapter 5 Copright 25 MGraw-Hill 6 Converion from Deimal to Binar Unit of Memor/Storage Binar digit = bit (little b ) Bte = 8 bit (apital B ) KB = 2 bte MB = 2 2 bte GB = 2 3 bte TB = 2 4 bte Fundamental of Digital Logi: Chapter 5 Copright 25 MGraw-Hill 7 8

3 Carr Half-Adder + Sum Deompoed Full-Adder i i HA i HA i + i (a) The four poible ae (a) Blok diagram Carr Sum i i i i i + i FA i i (b) Truth table i + HA (b) Detailed diagram i () Smbol () Ciruit (d) Graphial mbol Fundamental of Digital Logi: Chapter 5 Copright 25 MGraw-Hill 9 Fundamental of Digital Logi: Chapter 5 Copright 25 MGraw-Hill VHDL Code for Full Adder USE ieee.td_logi_64.all ; n n Ripple-Carr Adder ENTITY fulladd IS PORT ( Cin, a, b : IN STD_LOGIC ;, Cout : OUT STD_LOGIC ) ; END fulladd ; n FA n 2 FA FA ARCHITECTURE LogiFun OF fulladd IS <= a XOR b XOR Cin ; Cout <= (a AND b) OR (Cin AND a) OR (Cin AND b) ; END LogiFun ; n MSB poition Start from the LSB to the MSB LSB poition VHDL an be ued to deribe the truture a well Dela equal n t where t i the dela through one full-adder iruit Fundamental of Digital Logi: Chapter 5 Copright 25 MGraw-Hill Fundamental of Digital Logi: Chapter 5 Copright 25 MGraw-Hill 2

4 USE ieee.td_logi_64.all ; 4-Bit Ripple-Carr Adder Integer Repreentation ENTITY adder4 IS PORT ( Cin : IN STD LOGIC ; a3, a2, a, a : IN STD_LOGIC ; b3, b2, b, b : IN STD_LOGIC ; 3, 2,, : OUT STD_LOGIC ; Cout : OUT STD_LOGIC ) ; END adder4 ; ARCHITECTURE Struture OF adder4 IS SIGNAL, 2, 3 : STD_LOGIC ; COMPONENT fulladd PORT ( Cin, a, b : IN STD_LOGIC ;, Cout : OUT STD_LOGIC ) ; END COMPONENT ; tage: fulladd PORT MAP ( Cin, a, b,, ) ; tage: fulladd PORT MAP (, a, b,, 2 ) ; tage2: fulladd PORT MAP ( 2, a2, b2, 2, 3 ) ; tage3: fulladd PORT MAP ( Cin => 3, Cout => Cout, a => a3, b => b3, => 3 ) ; END Struture ; Can ue individual bit intead of a bu Thi verion mimi the trutural onnetion of full adder within the 4-bit adder Component port map et the internal onnetion b n b b Fundamental of Digital Logi: Chapter 5 Copright 25 MGraw-Hill 3 Fundamental of Digital Logi: Chapter 5 Copright 25 MGraw-Hill 4 MSB Magnitude (a) Unigned number b n b n 2 b b Sign denote + denote MSB Magnitude (b) Signed number Negative Binar Number Signed magnitude Leftmot bit i ign, remaining bit are magnitude Two repreentation for zero Interpretation of 4-Bit Signed Integer One omplement (obolete) Invert all bit Two repreentation for zero Two omplement Invert all bit and add Onl one repreentation for zero 5 Fundamental of Digital Logi: Chapter 5 Copright 25 MGraw-Hill 6

5 2 Complement Number Wheel Finite-Preiion Number Computer have fied number of digit to repreent value (reate et of valid value) Computation an lead to error Overflow: reult i larger than larget number in et Underflow: reult i maller than mallet number in et Computation ould reult in a number that annot be repreented (non-integer reult on integer mahine) Fundamental of Digital Logi: Chapter 5 Copright 25 MGraw-Hill 7 8 Determining Overflow Flag ( + 7) + ( + 2) ( + 9) + 4 = 3 = ( 7) + ( + 2) ( 5) + 4 = 3 = Adder/Subtrator Megafuntion ( + 7) + ( 2) + ( 7) + ( 2) + ( + 5) 4 = 3 = ( 9) 4 = 3 = Carr into MSB mut equal arr out of MSB (XOR gate) Fundamental of Digital Logi: Chapter 5 Copright 25 MGraw-Hill 9 Fundamental of Digital Logi: Chapter 5 Copright 25 MGraw-Hill 2

6 n Adder/Subtrator Ciruit n Add Sub ontrol Repreentation of Number in VHDL Ue a bu delaration SIGNAL C: td_logi_vetor(2 downto ) deribe a 3-bit bu where C(2) i mot ignifiant bit and C() i leat ignifiant bit SIGNAL C: td_logi_vetor( to 2) i alo a 3-bit bu, but C() i MSB, C(2) i LSB ALWAYS ue 'downto' in thi la n n -bit adder A ignal aignment an be done in man wa: C <= ""; aign all three bit C(2) <= ''; aign onl bit #2 C( downto ) <= ""; aign two bit of the bu n Fundamental of Digital Logi: Chapter 5 Copright 25 MGraw-Hill 2 Copright 2 Dr. Bob Reee 22 4-Bit Adder with Multi-Bit Signal USE ieee.td_logi_64.all ; USE work.fulladd_pakage.all ; ENTITY adder4 IS PORT ( Cin : IN STD_LOGIC ; X, Y : IN STD_LOGIC_VECTOR(3 DOWNTO ) ; S : OUT STD_LOGIC_VECTOR(3 DOWNTO ) ; Cout : OUT STD_LOGIC ) ; END adder4 ; ARCHITECTURE Struture OF adder4 IS SIGNAL C : STD_LOGIC_VECTOR(3 DOWNTO ) ; tage: fulladd PORT MAP ( Cin, X(), Y(), S(), C() ) ; tage: fulladd PORT MAP ( C(), X(), Y(), S(), C(2) ) ; tage2: fulladd PORT MAP ( C(2), X(2), Y(2), S(2), C(3) ) ; tage3: fulladd PORT MAP ( C(3), X(3), Y(3), S(3), Cout ) ; END Struture ; VHDL Code for 6-Bit Adder USE ieee.td_logi_64.all ; USE ieee.td_logi_igned.all ; ENTITY adder6 IS PORT ( X, Y : IN STD_LOGIC_VECTOR(5 DOWNTO ) ; S : OUT STD_LOGIC_VECTOR(5 DOWNTO ) ) ; END adder6 ; ARCHITECTURE Behavior OF adder6 IS S <= X + Y ; END Behavior ; Ue the igned pakage to add ignal Fundamental of Digital Logi: Chapter 5 Copright 25 MGraw-Hill 23 Fundamental of Digital Logi: Chapter 5 Copright 25 MGraw-Hill 24

7 Uing the Arithmeti Pakage USE ieee.td_logi_64.all ; USE ieee.td_logi_arith.all ; ENTITY adder6 IS PORT ( Cin : IN STD_LOGIC ; X, Y : IN SIGNED(5 DOWNTO ) ; S : OUT SIGNED(5 DOWNTO ) ; Cout, Overflow : OUT STD_LOGIC ) ; END adder6 ; ARCHITECTURE Behavior OF adder6 IS SIGNAL Sum : SIGNED(6 DOWNTO ) ; Sum <= ('' & X) + Y + Cin ; S <= Sum(5 DOWNTO ) ; Cout <= Sum(6) ; Overflow <= Sum(6) XOR X(5) XOR Y(5) XOR Sum(5) ; END Behavior ; Uing Integer Signal ENTITY adder6 IS PORT ( X, Y : IN INTEGER RANGE TO ; S : OUT INTEGER RANGE TO ) ; END adder6 ; ARCHITECTURE Behavior OF adder6 IS S <= X + Y ; END Behavior ; Fundamental of Digital Logi: Chapter 5 Copright 25 MGraw-Hill 25 Fundamental of Digital Logi: Chapter 5 Copright 25 MGraw-Hill 26 Summar Calulator do an eellent job of onverting value among deimal, binar, otal, and headeimal tem 2 omplement i ued beaue it onl ha one repreentation for zero The arr hain i the ritial path for an adder iruit 27