1 Address space with memory mapped devices

Size: px
Start display at page:

Download "1 Address space with memory mapped devices"

Transcription

1 1 Address space with memory mapped devices In systems with memory mapped devices, the devices appear as regions of memory. The addresses that these devices occupy are determined by the system designer. Generally the memory occupied by these devices is referred to as registers, where each register is 32 bits. The system designer will supply documentation, called the register map, that describes the structure of these registers. These device registers should not be confused with the processor registers. The first type of device that we will deal with is the PIO (Parallel I/O) core device. A core in this case is a digital logic unit that transforms the actual signals of a device into the set of read/write registers presented to the programmer s view of the device. The PIO core supplied by Altera provides basic support for simple devices such as buttons, switches and LEDs. More information about the PIO core may be found in the Quartus II Handbook Volume 5: Embedded Peripherals manual (Chapter 13). Pay special attention to the register map section of the PIO core. Byte Address 0x0000 0x0010 0x0020 word Program & Data Memory 0x7FF0 0x8000 0x8810 0x8820 0x8830 0x8840 0x8850 LEDs Green Registers LEDs Red Registers Buttons Registers Switches Registers Seven Segment Registers SYSID Registers JTAG UART Regs Device Memory Figure 1. Memory Map of Lab 2 Address Space Figure 1 is a representation of the address space for Lab2. The on-chip memory from 0 to (0x7fff) is where the program and data reside. The five devices at addresses from through 0x8840 are separate instances of the PIO core. Each instance is represented to the NIOS II system as four 32-bit registers. Ref PIO core (The other two devices at addresses 0x8850 and 0x8858 are of a different type and are shown here only for completeness.) Page 1 of 10

2 Figure 2 is an example representing the flow of data from the actual switches device through the digital logic unit (Switches PIO Core) to the programmer s view of the switches, which is represented by the 16 bytes of information starting at address 0x8830. Similar flow diagrams can be developed for the other PIO devices. Switches Device x8810 0x8820 0x8830 0x8840 0x8850 LEDs Green Registers LEDs Red Registers Buttons Registers Switches Registers Seven Segment Registers SYSID Registers JTAG UART Regs Switches PIO Core Device Memory system.h. Figure 2. Switches (PIO) Device Mapping /* * onchip_memory_0/s1 configuration */ #define ONCHIP_MEMORY_0_S1_NAME "/dev/onchip_memory_0" #define ONCHIP_MEMORY_0_S1_TYPE "altera_avalon_onchip_memory2" #define ONCHIP_MEMORY_0_S1_BASE 0x #define ONCHIP_MEMORY_0_S1_SPAN #define ONCHIP_MEMORY_0_SIZE_MULTIPLE 1024 #define ONCHIP_MEMORY_0_SIZE_VALUE 32 #define ONCHIP_MEMORY_0_WRITEABLE 1 #define ONCHIP_MEMORY_0_GUI_RAM_BLOCK_TYPE "Automatic" #define ONCHIP_MEMORY_0_CONTENTS_INFO "QUARTUS_PROJECT_DIR/onchip_memory_0.hex SIMDIR/onchip_memory_0.dat " #define ONCHIP_MEMORY_0_INIT_CONTENTS_FILE "onchip_memory_0" #define ONCHIP_MEMORY_0_RAM_BLOCK_TYPE "M4K" #define ONCHIP_MEMORY_0_DUAL_PORT 0 #define ONCHIP_MEMORY_0_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0 #define ONCHIP_MEMORY_0_NON_DEFAULT_INIT_FILE_ENABLED 0. /* * led_green configuration */ #define LED_GREEN_NAME "/dev/led_green" #define LED_GREEN_TYPE "altera_avalon_pio" #define LED_GREEN_BASE 0x #define LED_GREEN_SPAN 16 #define LED_GREEN_HAS_IN 0 #define LED_GREEN_HAS_OUT 1 #define LED_GREEN_CAPTURE 0 #define LED_GREEN_EDGE_TYPE "NONE" #define LED_GREEN_HAS_TRI 0 #define LED_GREEN_IRQ_TYPE "NONE" #define LED_GREEN_DO_TEST_BENCH_WIRING 0 #define LED_GREEN_DRIVEN_SIM_VALUE 0x0000. Figure 3. Lab2 system.h excerpt Page 2 of 10

3 Altera Debug Client will automatically produce a system.h file each time that the.ptf is associated with a configuration. The system.h file represents information that C programs can use in order to access the devices for a particular system. Though the.h file cannot be used directly for assembly language programs, it provides insight into the devices connected to the system, and can be used to manually create a comparable file that is usable for assembly language. Figure 3 is an excerpt of the system.h file generated by Altera Debug Client for Lab2. (Note that Figure 1 was developed by investigating the contents of this system.h file.) Since we re working with assembly in Lab 2, we need to create the assembly language version of the system.h file. We will call this assembly language file the system.inc to distinguish it from the C language version. Figure 4 represents a template for the assembly language variant. As you can see, the C language variant of the.equ directive is #define macro. Note that the system.inc file in Figure 4 is only partially complete; you are to complete Lab2 system.inc before coming to lab. system.inc.equ MEMORY_START,0x0.equ MEMORY_SIZE,32768.equ STACK,MEMORY_START+MEMORY_SIZE.equ LEDS_GREEN,.equ LEDS_RED,0x????.equ BUTTONS,0x????.equ SWITCHES,0x????.equ SEVEN_SEG,0x????.equ SYSID,0x????.equ JTAG_UART,0x???? Figure 4. Lab2 system.inc Now let s take a closer look at the device registers for the green LEDs. The system.h definition, shown in Figure 5, provides information on the device name (highlighted in gray), type, address (highlighted in yellow), span (highlighted in blue), and other features. Figure 6 is a visual representation of the green LED registers, based on the information in the system.h. (Note that there are four registers, with 32-bits each.) /* * led_green configuration */ #define LED_GREEN_NAME "/dev/led_green" #define LED_GREEN_TYPE "altera_avalon_pio" #define LED_GREEN_BASE 0x #define LED_GREEN_SPAN 16 #define LED_GREEN_HAS_IN 0 #define LED_GREEN_HAS_OUT 1 #define LED_GREEN_CAPTURE 0 #define LED_GREEN_EDGE_TYPE "NONE" #define LED_GREEN_HAS_TRI 0 #define LED_GREEN_IRQ_TYPE "NONE" #define LED_GREEN_DO_TEST_BENCH_WIRING 0 #define LED_GREEN_DRIVEN_SIM_VALUE 0x0000 Figure 5. system.h definition for green LEDs LEDs Green Registers Figure 6. Visual representation of LED Green Registers (software perspective) Page 3 of 10

4 At this point we only know that the device takes 16 bytes of memory address space (LED_green_span), so the above offset representation is in bytes (+0, +4, +8, +12). However, additional information on the PIO device is available in the Quartus II Handbook (Q2H). The table below (from Q2H) shows us that, from a hardware perspective, the 16 bytes are really viewed as 4 words (or device registers). This register notation is shown in Figure 7. Taken from Quartus II Handbook. Refer to the PIO Core (Chaper 13) for more information. LEDs Green Registers +0 data +1 direction +2 interruptmask +3 edgecapture Figure 7. Register Notation (hardware perspective) Note, however, that programming instructions reference registers in terms of bytes, so the register offsets in Figure 7 must be re-interpreted as shown in Figure 6. Analyze the following instructions and how they will work. For example, the instruction ldwio r9,0(r8) will read from the data register at offset 0 and place the word from the device s data register into register r9. movia r8, ldwio r9,0(r8) # read from data register stwio r9,0(r8) # write to data register ldwio r10,4(r8) # read from direction register stwio r10,4(r8) # write to direction register ldwio r11,8(r8) # read from interruptmask register stwio r11,8(r8) # write to interruptmask register ldwio r12,12(r8) # read from edgecapture register stwio r12,12(r8) # write to edgecapture register (The appropriate usage of ldwio vs. stwio is dependent upon the type of PIO device and what result is required.) Further information about the configuration of a device can be found by scanning the lab2.ptf file, shown below. The MODULE definition for the led_green device reveals that the port has 9 active bits. Page 4 of 10

5 MODULE led_green { class = "altera_avalon_pio"; class_version = "6.0"; HDL_INFO { PORT_WIRING { PORT T in_port { direction = "input"; Is_Enabled = "0"; width = "9"; PORT out_port { direction = "output"; Is_Enabled = "1"; width = "9"; PORT bidir_port { direction = "inout"; Is_Enabled = "0"; width = "9"; SLAVE s1 { SYSTEM_BUILDER_INFO { WIZARD_SCRIPT_ARGUMENTS { Figure 8. Excerpt of lab2.ptf Since only 9 bits of the 32 are used, it is important to determine which are the ones being used. Figure 9 below represents a typical alignment of used and unused bits in the data register. LEDs Green Registers +0 data +1 direction +2 interruptmask +3 edgecapture LEDs Green Data Register UNUSED USED 8 0 Figure 9. Bit representation of green LEDs data register The following definitions (from the system.h file are also worth noting and comparing to other PIO devices to see how different features are represented. #define LED_GREEN_HAS_IN 0 #define LED_GREEN_HAS_OUT 1 #define LED_GREEN_CAPTURE 0 #define LED_GREEN_EDGE_TYPE "NONE" #define LED_GREEN_HAS_TRI 0 #define LED_GREEN_IRQ_TYPE "NONE" Page 5 of 10

6 Note that each PIO device utilizes 16 bytes as described in the system.h file, and each four bytes or word is considered a register. 2 Memory stack structure + examples Figure? shows a revised version of the memory address space to include the stack region of memory. The concept of a stack is to allow for dynamic reuse of memory. It allows us to utilize memory on a last-in-first-out basis. In the case of typical program/data organization, the stack starts at the end of writeable memory (actually the address after the end this address should never be written to), and grows in size by adjusting the stack pointer to lower memory addresses. In the figure below, the address for the stack pointer (sp) should be set to a value of (0x ) at initialization (which is the end of writeable memory in this case). At this point, the stack is considered empty. But as shown in this figure, the value for the sp is actually 0x7FE0. If 8 bytes of space is needed, then the stack pointer should be reduced by 8 and when no longer needed the sp should be increased by 8. As show the stack pointer register (sp) should contain the value 0x00007fe0 and reflects that 32 bytes of memory are allocated to the stack. When the stack is empty the value of sp should be 0x x0000 Memory Address Space Instr 1 Instr 2 Instr 3 0x0010 Program Memory Data 1 Data 2 Data 3 Data Memory Current sp Initial sp 0x7FD0 0x7FE0 0x7FF0 0x8000 Dynamic Stack Space Figure? Memory Address Space with Stack.equ MEMORY_START,0x0.equ MEMORY_SIZE,32768.equ STACK,MEMORY_START+MEMORY_SIZE Figure?. Excerpt of system.inc Figure? shows an excerpt of the system.inc file previously created. It reflects the starting location of memory as address 0x0 and the length of memory as (0x8000). The sum Page 6 of 10

7 of these two values should point just beyond the last accessible location of memory, in this case 0x The following assembly language instruction placed at the beginning of a program will initialize the stack pointer for subsequent usage. For compatibility the FP register is sometimes used in conjunction with the sp register. For our purposes we will not use the FP register until a later time. movia sp,stack To allocate and use memory on stack use the following instruction sequence addi sp, sp, -16 stw r16, 0(sp) stw r17, 4(sp) stw r4, 8(sp) stw ra,12(sp) To recover memory space and data stored on stack use the following instructions. ldw r16, 0(sp) ldw r17, 4(sp) ldw r4, 8(sp) ldw ra, 12(sp) addi sp, sp, 16 More details of stack usage will be given in class lecture. Before we go any further, let s create a template program that can be used for many future programs. The systems that we ve seen so far have the reset address set to the first address in memory, which (in the systems we ve seen) is 0x0. Another important address is the exception address. We will not cover the usage of this address until a later time, but the address that it is usually assigned is 0x20. In order to avoid any problems with this address, it is wise to relocate our program code to some location following the reset address and allow enough space for code. As a program is being assembled, a location counter is being maintained for each section (i.e..text and.data). In the template program shown below, for location 0x0 we place a to jump around the areas that we wish to preserve and to the location where our code does its work. Once the jump instruction is done, the location counter is updated to a value of 0x4. However, we can force the location counter to an absolute location with the usage of the.org directive. Since we know that it is possible to have exceptions and the processor will always jump to the exception address (0x20), we can place a eak instruction at this location to stop execution if an exception happens. By placing a.org 0x20 after the PROGRAM_START instruction, we can ensure that a eak is placed at address 0x20. Now, using the.org directive again we can reserve space for future code that will handle exceptions. It is unknown just how much space is needed, but it s handy to have the program Page 7 of 10

8 start location occur at a known location for debugging purposes. So, for now we choose address 0x100. With these considerations, we have a template for future programs that will work until such time as we need to handle interrupts. # file: template.s.include "system.inc".text.global _start _start: PROGRAM_START.org 0x20 eak.org 0x100 PROGRAM_START: movia sp,stack # optional if exception happens # optional this will stop exec # nice place to start program # Setup the stack pointer # main code goes here PROGRAM_END: eak PROGRAM_END.data.end 3 Register usage Before going much further, we need to consider the usage of the general purpose registers as they relate to function calls. We will define the following register group names. Group Usage Registers M-Regs Main routine registers r16-r23 R-Regs Return values from function r2-r3 A-Regs Arguments to function r4-r7 S-Regs Suoutine (function) registers r8-r15 Usage of these register conventions will cover any applications that only have function call depths 1 layer deep. More complex situations will be explained in lecture. Why are the.global directives needed in the Code 2 suoutines? Notice that the system.inc included is no longer needed in the top level program. One of the first steps in writing good code is the eaking up of the code into layers. By isolating the code involved with different hardware devices into separate modules, we can hide the details of working with a device inside of the module and provide the basis of hardware abstraction. In this example the details of which bits are associated with a specific switch or LED have not been hidden, but that can come later. Page 8 of 10

9 4 Suoutines You are to learn how suoutines work from Code 1 and Code 2, on the following page. Note that suoutine modules do not need all of the startup code as the main routine. Observe that values are passed to the suoutine via r4 and values are returned via r2. Now, try to send the data from switches to seven segment LEDs. Once you have done so, you need to create a new assembly suoutine to interface to the green LEDs and tie in to the main assembly program. Compare Code 1 and Code 2 on the following page. What are the main differences between Code 1 and Code 2? # file: lab2_dev1.s.include "system.inc".text.global _start _start:.org 0x100 PROGRAM_START: PROGRAM_START loop: call SWITCHES_Get mov r4,r2 call LEDR_Set loop_end: loop PROGRAM_END: eak PROGRAM_END SWITCHES_Get: movia r8,switches ldwio r2,0(r8) ret LEDR_Set: movia r8,leds_red stwio r4,0(r8) ret.end Code 1 # file: lab2_dev2.s.text.global _start _start:.org 0x100 PROGRAM_START: PROGRAM_START loop: call SWITCHES_Get mov r4,r2 call LEDR_Set loop_end: PROGRAM_END: eak.end Code 2 loop PROGRAM_END # file: SWITCHES.s.include "system.inc".text.global SWITCHES_Get SWITCHES_Get: movia r8,switches ldwio r2,0(r8) ret.end # file: LEDR.s.include "system.inc".text.global LEDR_Set LEDR_Set: movia r8,leds_red stwio r4,0(r8) ret.end Page 9 of 10

10 5 Macros Consider the assembly code below. This assembly programs sets up a 32-bit number using the movia instruction. The next two instructions shift the 32-bit register and mask with 0b1111 (same as 0xf). This gets 4-bit ( 6 ) out of the 32-bit number. movia r4,0x srli r2, r4, 8 andi r2, r2, 0b1111 The following assembly code sets up a 32-bit number using movia insruction again, then replace 6 with b. movia r2,0x movi r4,0xab andi r4, r4, 0b1111 slli r4, r4, 8 movi r3, 0b1111 slli r3, r3, 8 nor r3, zero, r3 and r2, r2, r3 or r2, r2, r4 Now copy the following assembly code into the template again. Run and observe. Now get and replace different bits. The macros needed to be inserted before the.text directive in the template..macro getbits rego, regi, offset, mask srli \rego, \regi, \offset andi \rego, \rego, \mask.endm.macro putbits rego, regi, regw, offset,mask andi \regi, \regi, \mask slli \regi,\regi,\offset movi \regw,\mask slli \regw, \regw, \offset nor \regw, zero, \regw and \rego,\rego,\regw or \rego,\rego,\regi.endm movia r4,0x getbits r2,r4,8,0xf movi r3,0xa putbits r4,r3,r5,8,0xf More example code can be found lab zip file. Page 10 of 10

E 332L Microprocessors Lab (Fall 2007) Week 3

E 332L Microprocessors Lab (Fall 2007) Week 3 E 332L Microprocessors Lab (Fall 2007) Week 3 Objective: In this lab, you will learn how to interface to LEDs, Seven Segment LEDs, and switches. You will also learn how to write assembly suoutines. Note

More information

Detailed Nios II Exception Process

Detailed Nios II Exception Process Detailed Nios II Exception Process When an exception is triggered, the CPU does the following steps automatically: 1. Copy the contents of status to estatus to save pre-exception state 2. Clear (0) PIE

More information

1. Number Conversions [8 marks]

1. Number Conversions [8 marks] 1. Number Conversions [8 marks] a. convert the decimal number 42 to a 16-bit signed integer in binary 0b0000 0000 0010 1010 b. convert the 8-bit number 0x42 to a 16-bit signed integer in binary 0b0000

More information

Basic Computer System for the Altera DE0-Nano Board. 1 Introduction. 2 DE0-Nano Basic Computer Contents. 2.1 Nios II Processor. For Quartus II 13.

Basic Computer System for the Altera DE0-Nano Board. 1 Introduction. 2 DE0-Nano Basic Computer Contents. 2.1 Nios II Processor. For Quartus II 13. Basic Computer System for the Altera DE0-Nano Board For Quartus II 13.0 1 Introduction This document describes a simple computer system that can be implemented on the Altera DE0-Nano development and education

More information

I expect you to understand everything discussed prior to this page. In particular:

I expect you to understand everything discussed prior to this page. In particular: A NOTE TO 259 STUDENTS: Interrupts involve a lot of details. The details presented after this page provide further background on exactly what happens at the CPU logic and assembly code levels. This may

More information

Basic Computer System for the Altera DE1 Board. 1 Introduction. 2 DE1 Basic Computer Contents. 2.1 Nios II Processor.

Basic Computer System for the Altera DE1 Board. 1 Introduction. 2 DE1 Basic Computer Contents. 2.1 Nios II Processor. Basic Computer System for the Altera DE1 Board For Quartus II 8 1 Introduction This document describes a simple computer system that can be implemented on the Altera DE1 development and education board.

More information

DE2-115 Computer System. 1 Introduction. 2 DE2-115 Computer Contents. 2.1 Nios II Processor. For Quartus Prime 16.1

DE2-115 Computer System. 1 Introduction. 2 DE2-115 Computer Contents. 2.1 Nios II Processor. For Quartus Prime 16.1 DE2-115 Computer System For Quartus Prime 16.1 1 Introduction This document describes a computer system that can be implemented on the Intel DE2-115 development and education board. This system, called

More information

Part 1: Start up. Part 2: Add Instruction. Part 3: Another way to get data into a register

Part 1: Start up. Part 2: Add Instruction. Part 3: Another way to get data into a register Part 1: Start up Power on the DE2 (Lab 0 showed you how), and begin the project by doing the following: Create new project directory Copy lab1sof and lab1ptf to the new directory Copy code provided (lab01?s)

More information

Last Name (in case pages get detached): UNIVERSITY OF TORONTO FACULTY OF APPLIED SCIENCE AND ENGINEERING MIDTERM EXAMINATION, MARCH 2011

Last Name (in case pages get detached): UNIVERSITY OF TORONTO FACULTY OF APPLIED SCIENCE AND ENGINEERING MIDTERM EXAMINATION, MARCH 2011 Page 1 of 13 UNIVERSITY OF TORONTO FACULTY OF APPLIED SCIENCE AND ENGINEERING MIDTERM EXAMINATION, MARCH 2011 ECE243H1 S COMPUTER ORGANIZATION Exam Type: D Duration: 2 Hours Prof.s Anderson, Enright Jerger,

More information

Debugging of Application Programs on Altera s DE-Series Boards. 1 Introduction

Debugging of Application Programs on Altera s DE-Series Boards. 1 Introduction Debugging of Application Programs on Altera s DE-Series Boards 1 Introduction This tutorial presents some basic concepts that can be helpful in debugging of application programs written in the Nios II

More information

1 Do not confuse the MPU with the Nios II memory management unit (MMU). The MPU does not provide memory mapping or management.

1 Do not confuse the MPU with the Nios II memory management unit (MMU). The MPU does not provide memory mapping or management. Nios II MPU Usage March 2010 AN-540-1.0 Introduction This application note covers the basic features of the Nios II processor s optional memory protection unit (MPU), describing how to use it without the

More information

University of Toronto Faculty of Applied Science and Engineering Department of Electrical and Computer Engineering Final Examination

University of Toronto Faculty of Applied Science and Engineering Department of Electrical and Computer Engineering Final Examination University of Toronto Faculty of Applied Science and Engineering Department of Electrical and Computer Engineering Final Examination ECE 253F - Digital and Computer Systems Friday December 10, 2010 Duration:

More information

9. Cache and Tightly-Coupled Memory

9. Cache and Tightly-Coupled Memory 9. Cache and Tightly-Coupled Memory February 2011 NII52007-10.1.0 NII52007-10.1.0 Introduction Nios II processor cores can contain instruction and data caches. This chapter discusses cache-related issues

More information

Last Name (in case pages get detached): UNIVERSITY OF TORONTO FACULTY OF APPLIED SCIENCE AND ENGINEERING FINAL EXAMINATION, APRIL 2011

Last Name (in case pages get detached): UNIVERSITY OF TORONTO FACULTY OF APPLIED SCIENCE AND ENGINEERING FINAL EXAMINATION, APRIL 2011 Page 1 of 17 UNIVERSITY OF TORONTO FACULTY OF APPLIED SCIENCE AND ENGINEERING FINAL EXAMINATION, APRIL 2011 ECE243H1 S COMPUTER ORGANIZATION Exam Type: D Duration: 2.5 Hours Prof.s Anderson, Enright Jerger,

More information

Programming Model 2 A. Introduction

Programming Model 2 A. Introduction Programming Model 2 A. Introduction Objectives At the end of this lab you should be able to: Use direct and indirect addressing modes of accessing data in memory Create an iterative loop of instructions

More information

Chapter 2. Instructions:

Chapter 2. Instructions: Chapter 2 1 Instructions: Language of the Machine More primitive than higher level languages e.g., no sophisticated control flow Very restrictive e.g., MIPS Arithmetic Instructions We ll be working with

More information

Xuan Guo. Lecture XIX: Subroutines (2) CSC 3210 Computer Organization and Programming Georgia State University. March 31, 2015.

Xuan Guo. Lecture XIX: Subroutines (2) CSC 3210 Computer Organization and Programming Georgia State University. March 31, 2015. CSC 3210 Computer Organization and Programming Georgia State University March 31, 2015 This lecture Plan for the lecture: Recap: Register Saving Subroutine Linkage call instruction jmpl instruction ret

More information

9. PIO Core. Core Overview. Functional Description

9. PIO Core. Core Overview. Functional Description 9. PIO Core NII51007-9.0.0 Core Overview The parallel input/output (PIO) core with Avalon interface provides a memory-mapped interface between an Avalon Memory-Mapped (Avalon-MM) slave port and general-purpose

More information

Instructions: Assembly Language

Instructions: Assembly Language Chapter 2 Instructions: Assembly Language Reading: The corresponding chapter in the 2nd edition is Chapter 3, in the 3rd edition it is Chapter 2 and Appendix A and in the 4th edition it is Chapter 2 and

More information

Laboratory Exercise 4

Laboratory Exercise 4 Laboratory Exercise Input/Output in an Embedded System The purpose of this exercise is to investigate the use of devices that provide input and output capabilities for a processor. There are two basic

More information

University of Massachusetts Amherst Computer Systems Lab 1 (ECE 354) LAB 1 Reference Manual

University of Massachusetts Amherst Computer Systems Lab 1 (ECE 354) LAB 1 Reference Manual University of Massachusetts Amherst Computer Systems Lab 1 (ECE 354) LAB 1 Reference Manual Lab 1: Using NIOS II processor for code execution on FPGA Objectives: 1. Understand the typical design flow in

More information

Chapter 7 Subroutines. Richard P. Paul, SPARC Architecture, Assembly Language Programming, and C

Chapter 7 Subroutines. Richard P. Paul, SPARC Architecture, Assembly Language Programming, and C Chapter 7 Subroutines Richard P. Paul, SPARC Architecture, Assembly Language Programming, and C 2 Subroutines Subroutines allow us to either to repeat a computation or to repeat the computation with different

More information

Embedded Computing Platform. Architecture and Instruction Set

Embedded Computing Platform. Architecture and Instruction Set Embedded Computing Platform Microprocessor: Architecture and Instruction Set Ingo Sander ingo@kth.se Microprocessor A central part of the embedded platform A platform is the basic hardware and software

More information

Grundlagen Microcontroller Processor Core. Günther Gridling Bettina Weiss

Grundlagen Microcontroller Processor Core. Günther Gridling Bettina Weiss Grundlagen Microcontroller Processor Core Günther Gridling Bettina Weiss 1 Processor Core Architecture Instruction Set Lecture Overview 2 Processor Core Architecture Computes things > ALU (Arithmetic Logic

More information

Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: MIPS Instruction Set Architecture

Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: MIPS Instruction Set Architecture Computer Science 324 Computer Architecture Mount Holyoke College Fall 2009 Topic Notes: MIPS Instruction Set Architecture vonneumann Architecture Modern computers use the vonneumann architecture. Idea:

More information

Assembly Language Programming. CPSC 252 Computer Organization Ellen Walker, Hiram College

Assembly Language Programming. CPSC 252 Computer Organization Ellen Walker, Hiram College Assembly Language Programming CPSC 252 Computer Organization Ellen Walker, Hiram College Instruction Set Design Complex and powerful enough to enable any computation Simplicity of equipment MIPS Microprocessor

More information

Subroutines and the Stack

Subroutines and the Stack 3 31 Objectives: A subroutine is a reusable program module A main program can call or jump to the subroutine one or more times The stack is used in several ways when subroutines are called In this lab

More information

ece4750-tinyrv-isa.txt

ece4750-tinyrv-isa.txt ========================================================================== Tiny RISC-V Instruction Set Architecture ========================================================================== # Author :

More information

University of Toronto Faculty of Applied Science and Engineering

University of Toronto Faculty of Applied Science and Engineering Print: First Name:............................. Last Name:............................. Student Number:............................................... University of Toronto Faculty of Applied Science and

More information

COMP 303 Computer Architecture Lecture 3. Comp 303 Computer Architecture

COMP 303 Computer Architecture Lecture 3. Comp 303 Computer Architecture COMP 303 Computer Architecture Lecture 3 Comp 303 Computer Architecture 1 Supporting procedures in computer hardware The execution of a procedure Place parameters in a place where the procedure can access

More information

Compiling Code, Procedures and Stacks

Compiling Code, Procedures and Stacks Compiling Code, Procedures and Stacks L03-1 RISC-V Recap Computational Instructions executed by ALU Register-Register: op dest, src1, src2 Register-Immediate: op dest, src1, const Control flow instructions

More information

ECE332, Week 8. Topics. October 15, Exceptions. Hardware Interrupts Software exceptions

ECE332, Week 8. Topics. October 15, Exceptions. Hardware Interrupts Software exceptions ECE332, Week 8 October 15, 2007 1 Topics Exceptions Hardware Interrupts Software exceptions Unimplemented instructions Software traps Other exceptions 2 1 Exception An exception is a transfer of control

More information

Student # (use if pages get separated)

Student # (use if pages get separated) UNIVERSITY OF TORONTO FACULTY OF APPLIED SCIENCE AND ENGINEERING FINAL EXAMINATION, APRIL 2016 DURATION 2 and ½ hrs Second Year - ECE ECE243H1 S COMPUTER ORGANIZATION Exam Type: D Examiners P. Anderson,

More information

Tutorial 1: Programming Model 1

Tutorial 1: Programming Model 1 Tutorial 1: Programming Model 1 Introduction Objectives At the end of this lab you should be able to: Use the CPU simulator to create basic CPU instructions Use the simulator to execute the basic CPU instructions

More information

8. Instruction Set Reference

8. Instruction Set Reference 8. Instruction Set Reference NII51017-7.1.0 Introduction This section introduces the Nios II instruction-word format and provides a detailed reference of the Nios II instruction set. This chapter contains

More information

Topic Notes: MIPS Instruction Set Architecture

Topic Notes: MIPS Instruction Set Architecture Computer Science 220 Assembly Language & Comp. Architecture Siena College Fall 2011 Topic Notes: MIPS Instruction Set Architecture vonneumann Architecture Modern computers use the vonneumann architecture.

More information

Laboratory Exercise 5

Laboratory Exercise 5 Laboratory Exercise 5 Bus Communication The purpose of this exercise is to learn how to communicate using a bus. In the designs generated by using Altera s SOPC Builder, the Nios II processor connects

More information

Procedures and Stacks

Procedures and Stacks Procedures and Stacks Daniel Sanchez Computer Science & Artificial Intelligence Lab M.I.T. March 15, 2018 L10-1 Announcements Schedule has shifted due to snow day Quiz 2 is now on Thu 4/12 (one week later)

More information

Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: MIPS Instruction Set Architecture

Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: MIPS Instruction Set Architecture Computer Science 324 Computer Architecture Mount Holyoke College Fall 2007 Topic Notes: MIPS Instruction Set Architecture vonneumann Architecture Modern computers use the vonneumann architecture. Idea:

More information

Instruction Set Architectures Part I: From C to MIPS. Readings:

Instruction Set Architectures Part I: From C to MIPS. Readings: Instruction Set Architectures Part I: From C to MIPS Readings: 2.1-2.14 1 Goals for this Class Understand how CPUs run programs How do we express the computation the CPU? How does the CPU execute it? How

More information

CSCI341. Lecture 22, MIPS Programming: Directives, Linkers, Loaders, Memory

CSCI341. Lecture 22, MIPS Programming: Directives, Linkers, Loaders, Memory CSCI341 Lecture 22, MIPS Programming: Directives, Linkers, Loaders, Memory REVIEW Assemblers understand special commands called directives Assemblers understand macro commands Assembly programs become

More information

Today s Menu. >Use the Internal Register(s) >Use the Program Memory Space >Use the Stack >Use global memory

Today s Menu. >Use the Internal Register(s) >Use the Program Memory Space >Use the Stack >Use global memory Today s Menu Methods >Use the Internal Register(s) >Use the Program Memory Space >Use the Stack >Use global memory Look into my See examples on web-site: ParamPassing*asm and see Methods in Software and

More information

Memory Usage 0x7fffffff. stack. dynamic data. static data 0x Code Reserved 0x x A software convention

Memory Usage 0x7fffffff. stack. dynamic data. static data 0x Code Reserved 0x x A software convention Subroutines Why we use subroutines more modular program (small routines, outside data passed in) more readable, easier to debug code reuse i.e. smaller code space Memory Usage A software convention stack

More information

Programming the ARM. Computer Design 2002, Lecture 4. Robert Mullins

Programming the ARM. Computer Design 2002, Lecture 4. Robert Mullins Programming the ARM Computer Design 2002, Lecture 4 Robert Mullins 2 Quick Recap The Control Flow Model Ordered list of instructions, fetch/execute, PC Instruction Set Architectures Types of internal storage

More information

CENG3420 Lecture 03 Review

CENG3420 Lecture 03 Review CENG3420 Lecture 03 Review Bei Yu byu@cse.cuhk.edu.hk 2017 Spring 1 / 38 CISC vs. RISC Complex Instruction Set Computer (CISC) Lots of instructions of variable size, very memory optimal, typically less

More information

Machine Language Instructions Introduction. Instructions Words of a language understood by machine. Instruction set Vocabulary of the machine

Machine Language Instructions Introduction. Instructions Words of a language understood by machine. Instruction set Vocabulary of the machine Machine Language Instructions Introduction Instructions Words of a language understood by machine Instruction set Vocabulary of the machine Current goal: to relate a high level language to instruction

More information

Chapter 3. Instructions:

Chapter 3. Instructions: Chapter 3 1 Instructions: Language of the Machine More primitive than higher level languages e.g., no sophisticated control flow Very restrictive e.g., MIPS Arithmetic Instructions We ll be working with

More information

Laboratory Exercise 3 Comparative Analysis of Hardware and Emulation Forms of Signed 32-Bit Multiplication

Laboratory Exercise 3 Comparative Analysis of Hardware and Emulation Forms of Signed 32-Bit Multiplication Laboratory Exercise 3 Comparative Analysis of Hardware and Emulation Forms of Signed 32-Bit Multiplication Introduction All processors offer some form of instructions to add, subtract, and manipulate data.

More information

CPE 323 MSP430 INSTRUCTION SET ARCHITECTURE (ISA)

CPE 323 MSP430 INSTRUCTION SET ARCHITECTURE (ISA) CPE 323 MSP430 INSTRUCTION SET ARCHITECTURE (ISA) Aleksandar Milenković Email: milenka@uah.edu Web: http://www.ece.uah.edu/~milenka Objective Introduce MSP430 Instruction Set Architecture (Class of ISA,

More information

appendix a The LC-3 ISA A.1 Overview

appendix a The LC-3 ISA A.1 Overview A.1 Overview The Instruction Set Architecture (ISA) of the LC-3 is defined as follows: Memory address space 16 bits, corresponding to 2 16 locations, each containing one word (16 bits). Addresses are numbered

More information

Chapter 2. Instruction Set Architecture (ISA)

Chapter 2. Instruction Set Architecture (ISA) Chapter 2 Instruction Set Architecture (ISA) MIPS arithmetic Design Principle: simplicity favors regularity. Why? Of course this complicates some things... C code: A = B + C + D; E = F - A; MIPS code:

More information

Simulating Nios II Embedded Processor Designs

Simulating Nios II Embedded Processor Designs Simulating Nios II Embedded Processor Designs May 2004, ver.1.0 Application Note 351 Introduction The increasing pressure to deliver robust products to market in a timely manner has amplified the importance

More information

Rui Wang, Assistant professor Dept. of Information and Communication Tongji University.

Rui Wang, Assistant professor Dept. of Information and Communication Tongji University. Instructions: ti Language of the Computer Rui Wang, Assistant professor Dept. of Information and Communication Tongji University it Email: ruiwang@tongji.edu.cn Computer Hierarchy Levels Language understood

More information

FALSIM. FALSIM is the name of the software application which consists of the FALCON-A assembler and the FALCON-A simulator. It runs under Windows XP.

FALSIM. FALSIM is the name of the software application which consists of the FALCON-A assembler and the FALCON-A simulator. It runs under Windows XP. Lecture Handouts Computer Architecture Appendix Reading Material Handouts Summary 1. Introduction to FALSIM 2. Preparing source files for FALSIM 3. Using FALSIM 4. FALCON-A assembly language techniques

More information

IS1200/IS1500 Computer Engineering

IS1200/IS1500 Computer Engineering IS1200/IS1500 Computer Engineering Laboratory Exercise nios2int Interrupts and Traps Incomplete work is only valid until 2015-05-31 Student's name in permanent ink: Latest update: 2014-11-06 Date: Demonstrations

More information

Do-While Example. In C++ In assembly language. do { z--; while (a == b); z = b; loop: addi $s2, $s2, -1 beq $s0, $s1, loop or $s2, $s1, $zero

Do-While Example. In C++ In assembly language. do { z--; while (a == b); z = b; loop: addi $s2, $s2, -1 beq $s0, $s1, loop or $s2, $s1, $zero Do-While Example In C++ do { z--; while (a == b); z = b; In assembly language loop: addi $s2, $s2, -1 beq $s0, $s1, loop or $s2, $s1, $zero 25 Comparisons Set on less than (slt) compares its source registers

More information

Introduction to the Altera SOPC Builder Using Verilog Designs. 1 Introduction

Introduction to the Altera SOPC Builder Using Verilog Designs. 1 Introduction Introduction to the Altera SOPC Builder Using Verilog Designs 1 Introduction This tutorial presents an introduction to Altera s SOPC Builder software, which is used to implement a system that uses the

More information

CS 316: Procedure Calls/Pipelining

CS 316: Procedure Calls/Pipelining CS 316: Procedure Calls/Pipelining Kavita Bala Fall 2007 Computer Science Cornell University Announcements PA 3 IS out today Lectures on it this Fri and next Tue/Thu Due on the Friday after Fall break

More information

Lecture 5: Procedure Calls

Lecture 5: Procedure Calls Lecture 5: Procedure Calls Today s topics: Memory layout, numbers, control instructions Procedure calls 1 Memory Organization The space allocated on stack by a procedure is termed the activation record

More information

Shift and Rotate Instructions

Shift and Rotate Instructions Shift and Rotate Instructions Shift and rotate instructions facilitate manipulations of data (that is, modifying part of a 32-bit data word). Such operations might include: Re-arrangement of bytes in a

More information

8. Instruction Set Reference

8. Instruction Set Reference 8. NII51017-10.0.0 Introduction This section introduces the Nios II instruction word format and provides a detailed reference of the Nios II instruction set. This chapter contains the following sections:

More information

ELEC / Computer Architecture and Design Fall 2013 Instruction Set Architecture (Chapter 2)

ELEC / Computer Architecture and Design Fall 2013 Instruction Set Architecture (Chapter 2) ELEC 5200-001/6200-001 Computer Architecture and Design Fall 2013 Instruction Set Architecture (Chapter 2) Victor P. Nelson, Professor & Asst. Chair Vishwani D. Agrawal, James J. Danaher Professor Department

More information

Implementing Procedure Calls

Implementing Procedure Calls 1 / 39 Implementing Procedure Calls February 18 22, 2013 2 / 39 Outline Intro to procedure calls Caller vs. callee Procedure call basics Calling conventions The stack Interacting with the stack Structure

More information

NET3001. Advanced Assembly

NET3001. Advanced Assembly NET3001 Advanced Assembly Arrays and Indexing supposed we have an array of 16 bytes at 0x0800.0100 write a program that determines if the array contains the byte '0x12' set r0=1 if the byte is found plan:

More information

Chapter 2. Computer Abstractions and Technology. Lesson 4: MIPS (cont )

Chapter 2. Computer Abstractions and Technology. Lesson 4: MIPS (cont ) Chapter 2 Computer Abstractions and Technology Lesson 4: MIPS (cont ) Logical Operations Instructions for bitwise manipulation Operation C Java MIPS Shift left >>> srl Bitwise

More information

Trap Vector Table. Interrupt Vector Table. Operating System and Supervisor Stack. Available for User Programs. Device Register Addresses

Trap Vector Table. Interrupt Vector Table. Operating System and Supervisor Stack. Available for User Programs. Device Register Addresses Chapter 1 The LC-3b ISA 1.1 Overview The Instruction Set Architecture (ISA) of the LC-3b is defined as follows: Memory address space 16 bits, corresponding to 2 16 locations, each containing one byte (8

More information

Laboratory Exercise 6

Laboratory Exercise 6 Laboratory Exercise 6 Using C code with the Nios II Processor This is an exercise in using C code with the Nios II processor in a DE-Series computer system. We will use the Intel FPGA Monitor Program software

More information

Part II Instruction-Set Architecture. Jan Computer Architecture, Instruction-Set Architecture Slide 1

Part II Instruction-Set Architecture. Jan Computer Architecture, Instruction-Set Architecture Slide 1 Part II Instruction-Set Architecture Jan. 211 Computer Architecture, Instruction-Set Architecture Slide 1 Short review of the previous lecture Performance = 1/(Execution time) = Clock rate / (Average CPI

More information

CS311 Lecture: The Architecture of a Simple Computer

CS311 Lecture: The Architecture of a Simple Computer CS311 Lecture: The Architecture of a Simple Computer Objectives: July 30, 2003 1. To introduce the MARIE architecture developed in Null ch. 4 2. To introduce writing programs in assembly language Materials:

More information

Stored Program Concept. Instructions: Characteristics of Instruction Set. Architecture Specification. Example of multiple operands

Stored Program Concept. Instructions: Characteristics of Instruction Set. Architecture Specification. Example of multiple operands Stored Program Concept Instructions: Instructions are bits Programs are stored in memory to be read or written just like data Processor Memory memory for data, programs, compilers, editors, etc. Fetch

More information

Low-Level C Programming

Low-Level C Programming Low-Level C Programming CSEE W4840 Prof. Stephen A. Edwards Columbia University Spring 2008 Low-Level C Programming p. Goals Function is correct Source code is concise, readable, maintainable Time-critical

More information

Designing with Nios II Processor for Hardware Engineers

Designing with Nios II Processor for Hardware Engineers Designing with Nios II Processor for Hardware Engineers Course Description This course provides all theoretical and practical know-how to design ALTERA SoC FPGAs based on the Nios II soft processor under

More information

CS61C : Machine Structures

CS61C : Machine Structures inst.eecs.berkeley.edu/~cs61c/su06 CS61C : Machine Structures Lecture #9: MIPS Procedures 2006-07-11 CS 61C L09 MIPS Procedures (1) Andy Carle C functions main() { int i,j,k,m;... i = mult(j,k);... m =

More information

MIPS%Assembly% E155%

MIPS%Assembly% E155% MIPS%Assembly% E155% Outline MIPS Architecture ISA Instruction types Machine codes Procedure call Stack 2 The MIPS Register Set Name Register Number Usage $0 0 the constant value 0 $at 1 assembler temporary

More information

Data Structure Layout. In HERA/Assembly

Data Structure Layout. In HERA/Assembly Data Structure Layout In HERA/Assembly Today, we re going to build some data structures in HERA First, a note on memory Registers are very fast RAM is relatively slow We use a cache to sit between them

More information

CS153: Compilers Lecture 8: Compiling Calls

CS153: Compilers Lecture 8: Compiling Calls CS153: Compilers Lecture 8: Compiling Calls Stephen Chong https://www.seas.harvard.edu/courses/cs153 Announcements Project 2 out Due Thu Oct 4 (7 days) Project 3 out Due Tuesday Oct 9 (12 days) Reminder:

More information

Today s topics. MIPS operations and operands. MIPS arithmetic. CS/COE1541: Introduction to Computer Architecture. A Review of MIPS ISA.

Today s topics. MIPS operations and operands. MIPS arithmetic. CS/COE1541: Introduction to Computer Architecture. A Review of MIPS ISA. Today s topics CS/COE1541: Introduction to Computer Architecture MIPS operations and operands MIPS registers Memory view Instruction encoding A Review of MIPS ISA Sangyeun Cho Arithmetic operations Logic

More information

Five classic components

Five classic components CS/COE0447: Computer Organization and Assembly Language Chapter 2 modified by Bruce Childers original slides by Sangyeun Cho Dept. of Computer Science Five classic components I am like a control tower

More information

Computer Science 2500 Computer Organization Rensselaer Polytechnic Institute Spring Topic Notes: MIPS Programming

Computer Science 2500 Computer Organization Rensselaer Polytechnic Institute Spring Topic Notes: MIPS Programming Computer Science 2500 Computer Organization Rensselaer Polytechnic Institute Spring 2009 Topic Notes: MIPS Programming We spent some time looking at the MIPS Instruction Set Architecture. We will now consider

More information

Lab 4 Prelab: MIPS Function Calls

Lab 4 Prelab: MIPS Function Calls Lab 4 Prelab: MIPS Function Calls Name: Sign the following statement: On my honor, as an Aggie, I have neither given nor received unauthorized aid on this academic work 1 Objective The main objective of

More information

We will study the MIPS assembly language as an exemplar of the concept.

We will study the MIPS assembly language as an exemplar of the concept. MIPS Assembly Language 1 We will study the MIPS assembly language as an exemplar of the concept. MIPS assembly instructions each consist of a single token specifying the command to be carried out, and

More information

Laboratory Exercise 7

Laboratory Exercise 7 Laboratory Exercise 7 Using Interrupts with C code The purpose of this exercise is to investigate the use of interrupts for the Nios II processor, using C code. To do this exercise you need to have a good

More information

CS401 - Computer Architecture and Assembly Language Programming Glossary By

CS401 - Computer Architecture and Assembly Language Programming Glossary By CS401 - Computer Architecture and Assembly Language Programming Glossary By absolute address : A virtual (not physical) address within the process address space that is computed as an absolute number.

More information

CISC 662 Graduate Computer Architecture. Lecture 4 - ISA MIPS ISA. In a CPU. (vonneumann) Processor Organization

CISC 662 Graduate Computer Architecture. Lecture 4 - ISA MIPS ISA. In a CPU. (vonneumann) Processor Organization CISC 662 Graduate Computer Architecture Lecture 4 - ISA MIPS ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,

More information

The SURE Architecture

The SURE Architecture The SURE Architecture David May: December 11, 2016 Background Computer programming is changing. Object-oriented languages, functional languages and others have accelerated software development. But these

More information

ARM Cortex-M4 Architecture and Instruction Set 1: Architecture Overview

ARM Cortex-M4 Architecture and Instruction Set 1: Architecture Overview ARM Cortex-M4 Architecture and Instruction Set 1: Architecture Overview M J Brockway January 25, 2016 UM10562 All information provided in this document is subject to legal disclaimers. NXP B.V. 2014. All

More information

Chapter 3 MIPS Assembly Language. Ó1998 Morgan Kaufmann Publishers 1

Chapter 3 MIPS Assembly Language. Ó1998 Morgan Kaufmann Publishers 1 Chapter 3 MIPS Assembly Language Ó1998 Morgan Kaufmann Publishers 1 Instructions: Language of the Machine More primitive than higher level languages e.g., no sophisticated control flow Very restrictive

More information

Systems Architecture I

Systems Architecture I Systems Architecture I Topics Assemblers, Linkers, and Loaders * Alternative Instruction Sets ** *This lecture was derived from material in the text (sec. 3.8-3.9). **This lecture was derived from material

More information

Course Administration

Course Administration Fall 2018 EE 3613: Computer Organization Chapter 2: Instruction Set Architecture Introduction 4/4 Avinash Karanth Department of Electrical Engineering & Computer Science Ohio University, Athens, Ohio 45701

More information

Introduction to the Altera Qsys System Integration Tool. 1 Introduction. For Quartus Prime 15.1

Introduction to the Altera Qsys System Integration Tool. 1 Introduction. For Quartus Prime 15.1 Introduction to the Altera Qsys System Integration Tool For Quartus Prime 15.1 1 Introduction This tutorial presents an introduction to Altera s Qsys system integration tool, which is used to design digital

More information

CISC 662 Graduate Computer Architecture. Lecture 4 - ISA

CISC 662 Graduate Computer Architecture. Lecture 4 - ISA CISC 662 Graduate Computer Architecture Lecture 4 - ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,

More information

MIPS Datapath. MIPS Registers (and the conventions associated with them) MIPS Instruction Types

MIPS Datapath. MIPS Registers (and the conventions associated with them) MIPS Instruction Types 1 Lecture 08 Introduction to the MIPS ISA + Procedure Calls in MIPS Longer instructions = more bits to address registers MIPS Datapath 6 bit opcodes... 2 MIPS Instructions are 32 bits More ways to address

More information

CS64 Week 5 Lecture 1. Kyle Dewey

CS64 Week 5 Lecture 1. Kyle Dewey CS64 Week 5 Lecture 1 Kyle Dewey Overview More branches in MIPS Memory in MIPS MIPS Calling Convention More Branches in MIPS else_if.asm nested_if.asm nested_else_if.asm Memory in MIPS Accessing Memory

More information

Module 8: Atmega32 Stack & Subroutine. Stack Pointer Subroutine Call function

Module 8: Atmega32 Stack & Subroutine. Stack Pointer Subroutine Call function Module 8: Atmega32 Stack & Subroutine Stack Pointer Subroutine Call function Stack Stack o Stack is a section of RAM used by the CPU to store information temporarily (i.e. data or address). o The CPU needs

More information

ECE232: Hardware Organization and Design

ECE232: Hardware Organization and Design ECE232: Hardware Organization and Design Lecture 4: Logic Operations and Introduction to Conditionals Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Overview Previously examined

More information

CS 61c: Great Ideas in Computer Architecture

CS 61c: Great Ideas in Computer Architecture MIPS Functions July 1, 2014 Review I RISC Design Principles Smaller is faster: 32 registers, fewer instructions Keep it simple: rigid syntax, fixed instruction length MIPS Registers: $s0-$s7,$t0-$t9, $0

More information

Using Tightly Coupled Memory with the Nios II Processor

Using Tightly Coupled Memory with the Nios II Processor Using Tightly Coupled Memory with the Nios II Processor TU-N2060305-1.2 This document describes how to use tightly coupled memory in designs that include a Nios II processor and discusses some possible

More information

Orange Coast College. Business Division. Computer Science Department CS 116- Computer Architecture. The Instructions

Orange Coast College. Business Division. Computer Science Department CS 116- Computer Architecture. The Instructions Orange Coast College Business Division Computer Science Department CS 116- Computer Architecture The Instructions 1 1 Topics: Assembly language, assemblers MIPS R2000 Assembly language Instruction set

More information

8. Instruction Set Reference

8. Instruction Set Reference 8. May 2011 NII51017-11.0.0 NII51017-11.0.0 This section introduces the Nios II instruction word format and provides a detailed reference of the Nios II instruction set. This chapter contains the following

More information

Simple benchmarks. Arithmetic Lessons

Simple benchmarks. Arithmetic Lessons Goals Like Writing English Low-Level C Programming CSEE W4840 Prof. Stephen A. Edwards Columbia University Spring 2007 Function is correct Source code is concise, readable, maintainable Time-critical sections

More information