University of Toronto Faculty of Applied Science and Engineering

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1 Print: First Name: Last Name: Student Number: University of Toronto Faculty of Applied Science and Engineering Final Examination April 29, 2014 ECE243 Computer Organization Examiners Phil Anderson, Natalie Enright Jerger, Glenn Gulak, Hamid Timorabadi 1. There are 7 questions and 23 pages. Do all questions. The total number of marks is 144. The duration of the test is 150 minutes. 2. ALL WORK IS TO BE DONE ON THESE SHEETS! Use the back of the pages if you need more space. You may also use the two blank sheets included at the end of the exam. Be sure to indicate clearly if your work continues elsewhere. 3. Please put your final solution in the box if one is provided. 4. Clear and concise answers will be considered more favourably than ones that ramble. Do not fill space just because it exists! 5. The exam is open book/open notes. 6. Calculators are not permitted. 7. Always give some explanations or reasoning for how you arrived at your solutions to help the marker understand your thinking. 8. To get full marks you must comment your code. 9. State your assumptions. Show your work. Use your time wisely as not all questions will require the same amount of time. If you think that assumptions must be made to answer a question, state them clearly. If there are multiple possibilities, comment that there are, explain why and then provide at least one possible answer and state the corresponding assumptions. 1 [20] 2 [32] 3 [30] 4 [16] 5 [16] 6 [15] 7 [15] Total [144] Page 1 of 23

2 1. Memory Design You are to design a 256 kilobyte, byte-addressable memory module that is attached to an 8-bit data bus. Recall that 1 KB = 1024B = 2 10 B. [8 marks] (a) The table below lists the memory chips that you can use to implement the memory module. For each memory chip type, 1. Memory)Design)[20)minutes]) give the number of rows and columns of memory chips required to implement the memory module when ) using only chips of that type. You)are)to)design)a)256)kilobyte,)byte>addressable)memory)module)that)is)attached)to)an)8>bit) bus.) Memory Chip Type Number of Rows (depth) Number of Columns (data width) ) a) [8) marks]) The) table) below) lists) the) memory) chips) that) you) can) use) to) implement) the) memory) 4K module.) 4 bits ) For) 64 each) chip) type,) give) the) number) 2 of) rows) and) columns) of) memory) chips)required)to)implement)the)memory)module)when)using)only)chips)of)that)type.) ) 16K 4 bit Memory'Chip' 16 Number'of' Number'of' 2 64K 2 bits 64K 4 bits Rows' 4K)x)4) ) ) Columns' K)x)4) ) ) K)x)2) ) ) 64K)x)4) ) ) [10 marks] (b) The ) memory module can hold a maximum of 4x4 memory chips as shown on the next page. From the table above, b) [8)marks])The)board)for)the)memory)module)can)hold)at)most)a)4x4)array)of)memory)chips) choose chip type so that will provide 256 kilobytes of memory using fewest chips possible. as)shown)on)the)next)page.))from)the)table)above,)choose)the)chip)type)so)that)the)board) Complete diagram on next by will) provide) 256) kilobytes) of) memory) using) the) fewest) chips) possible.) ) Complete) the) i. writing diagram)on)the)next)page)by)) inside each chip outline the chip type to be used; and ii. connecting i. writing)inside)each)chip)outline)the)chip)type)to)be)used;)and) the inputs and outputs address, data, and CS (chip select, also called enable) of each chip correctly ii. connecting) to address, the)inputs)and)outputs) ) data CS signalsaddress,)data,)and)cs)(chip)select)) ) of the module. is active low. Be sure of) each) to label chip) the address, datacorrectly)to)the)address)and)data)signals)of)the)module.))be)sure)to)label)the)address)and) and CS signals with the specific bits. data)signals.) The onlythe)only)other)parts)that)you)may)use)to)complete)the)diagram)are)any)of)the)following) other that you use to are any of following decoders: decoders:) ) ))S0) ) ))))))))))))))))))S0) 2) In))))))))))))))S0))) ) ))))))))))))))))))))4) In))))))))))))))S1) ))))))))))))))))3) In))))))))))))))S1) ))))))))))))))))) 2)x)4)))))))))S1) ) ) ))))))))))))))))))S2)) ) 3)x)8)))))))))S2)) ) Decoder))S2) ) ) ))))))))))))))))))S3) ) Decoder))S3) ) ))))))))))))))))))S3) ) ) ))))))))))))))))))S4) ) ))))))))))))))))))S4) ) ) ) ) ))))))))))))))))))S5) ) ))))))))))))))))))S5) ) ) ) ) 4)x)16))))))S6) ) ))))))))))))))))))S6) ) ) ) ) Decoder))S7) ) ))))))))))))))))))S7) ) ) ) ) ))))))))))))))))))S8) ) ) ) ) ) ) ))))))))))))))))))S9) ) ))))))))))))))))))) ) ) ) ) ))))))))))))))))S10) ) ) ) ) ) ) ))))))))))))))))S11) ) ))))))))))))))))) ) ) ) ) ))))))))))))))))S12) ) ) ) ) ) ) ))))))))))))))))S13) ) ))))))))))))))))) ) ) ) ) ))))))))))))))))S14) ) ))))))))))))))))) ) ) ) ) ))))))))))))))))S15) ) ))))))))))))))))) ) ) ) If)you)use)a)decoder,)make)sure)that)you)indicate)(on)the)next)page))what)kind)of)decoder)is) used)and)label)its)inputs)and)outputs)and)make)all)the)appropriate)interconnections.) If you use ) a decoder, make sure that you indicate (on the next page) what kind of decoder is used and label its inputs and outputs and make all the appropriate interconnections. Two copies of the diagram are given to you. You must cross out the diagram that you do not wish to have marked. Page 2 of 23

3 Address bus (A17- A0) (18 bits) A17- A16 C1 C2 C3 C4 A15- A0 A15- A0 64K x 4 64K x 4 A D CS R1 2x4 Dec S0 S1 S2 S3 64K x 4 64K x 4 R2 64K x 4 64K x 4 R3 64K x 4 64K x 4 R4 Data bus (D7- D0) (8 bits) D7- D4 D3- D0 Page 3 of 23

4 Address bus (A17- A0) (18 bits) C1 C2 C3 C4 A CS D R1 R2 R3 R4 Data bus (D7- D0) (8 bits) Page 4 of 23

5 [2 marks] (c) The byte 0b is stored at address 0x Using the coordinate system given in the diagram on the previous page (were C1 = column 1 and R1 = row 1), indicate using row and column coordinates, in which chip each bit is stored (i.e., give the coordinates of the appropriate chip rectangle (s) and the binary digits stored there). C1,R4: 1011 C2,R4: 0000 Page 5 of 23

6 2. Caches [2 marks] (a) In the context of cache memory, define Hit Rate. HitRate = Hits Hits+Misses = Hits T otalmemoryaccesses [2 marks] (b) In the context of cache memory, define Miss Penalty. Tag Search Time (time to determine if you have a cache miss) + Time to bring desired block from memory into the cache [12 marks] (c) Complete the following table: For a 32-bit address, width of Set number that Cache Configuration Tag Set Index Byte Offset address 0xC maps to Direct mapped, Block size = 32 bytes Cache size = 1024 bytes 2-way set associative Block size = 128 bytes Cache size = 128 blocks Fully associative Block size = 64 bytes of 1 or N/A Cache size = 128 kbytes Page 6 of 23

7 (d) Given the following cache and cache configuration: 2-way set associative 4 byte cache line 32 byte cache Tag Set Offset 10-bit address Write back and least recently used (LRU) replacement. The cache will always use the LRU bits to determine which line to fill (even if both lines are invalid). A line with an LRU bit of 0 means the line is more recently accessed than a line with LRU bit of 1. Block # Tag (binary) Data(3..0) Valid Dirty LRU Set Index = A B A B Set Index = A 59 BC A3 95 CB Set Index = EE EE EE EE FD Set Index = A4 4A F F You will be given a list of memory operations. The accesses do not occur one after another. You should assume that before each question, the state of the cache is as given above. In the space given, fill in the effects of the operation and give the state of the affected line after the cache operation. You should fill in the information using the same format as given in the example below. MM is used to indicate a byte from memory. Operation: CPU Reads 1 byte from 0x360 (Example) Address: 0b Fetch from memory? No Yes, from 0x360 to 0x363 Hit (H) or Miss (M): M Writeback: No Value returned: MM Cache State Block # Tag (binary) Data Valid Dirty Set Index = MM MM MM MM 1 0 [4 marks] i. Operation: CPU writes 0xAA to 0x24A Address: 0b Fetch from memory? No Yes, from 0x248 to 0x24B Hit (H) or Miss (M): M Writeback: No Value returned: None Cache State Block # Tag (binary) Data Valid Dirty Set Index = MM AA MM MM 1 1 Page 7 of 23

8 [4 marks] ii. Operation: CPU reads 1 byte from 0x24C Address: 0b Fetch from memory? No Yes, from to Hit (H) or Miss (M): H Writeback: No Value returned: 65 Cache State Block # Tag (binary) Data Valid Dirty Set Index = A4 4A [4 marks] iii. Operation: CPU reads 1 byte from 0x266 Address: 0b Fetch from memory? No Yes, from 0x264 to 0x267 Hit (H) or Miss (M): M Writeback: No Value returned: MM Cache State Block # Tag (binary) Data Valid Dirty Set Index = MM MM MM MM 1 0 [4 marks] iv. Operation: CPU writes 0xBE to 0x276 Address: 0b Fetch from memory? No Yes, from to Hit (H) or Miss (M): H Writeback: No Value returned: None Cache State Block # Tag (binary) Data Valid Dirty Set Index = A3 BE CB Page 8 of 23

9 3. Multi-Cycle CPU [7 marks] (a) Considering the multi-cycle CPU implementation from lecture, clearly write the values of the control signals for implementing the following in 1 cycle: PC = PC + 1 AluOut = PC + 1 MDR = MEM[R2] Note: Use as many don t cares as possible. All unaffected registers should remain unchanged. PCWrite = 1 AddrSel = 0 IRLoad = 0 MDRLoad = 1 RFWrite = 0 R1Sel = X R1R2Load = 0 ALU1 = 0 ALU2 = 001 AluOutWrite = 1 RegIn = ALUop = X 000 (for ADD) MemRead = 1 MemWrite = 0 The multicycle diagram is included for your reference. R1R2Load AluOutWrite 1 0 Page 9 of 23

10 [6 marks] (b) As discussed in lectures, all instructions in the multi-cycle CPU implementation perform the same operations in the first two cycles, i.e. Cycle 1: IR = Mem[PC], PC = PC + 1 Cycle 2: R1 = RF[IR7..6], R2 = RF[IR5..4] If Cycle 2 is changed to: Cycle 2: R1 = RF[1], R2 = RF[IR5..4] Then how many cycles are needed to execute the following instructions with this change to the multi-cycle implementation. These instructions have the following cycle counts in the original (lecture) implementation: BZ (3 cycles), ORI (5 cycles), ADD (4 cycles). Your answer should be the minimum number of cycle required to execute the instructions. Write your answer in the space provided below: BZ: 3 cycles ORI: 4 cycles ADD: 5 cycles Page 10 of 23

11 [12 marks] (c) As discussed in lectures, the following instruction: Load R1, (R2) requires four cycles to implement as shown in the table below. List in this table, the actions per cycle for a new copy instruction given by: copy (R1), (R2) where copy performs: mem[r1] = mem[r2] that copies the memory value from one address provided by R2 to to another address given by R1. Your answer should implement this instruction in the minimum number of cycles. Cycle 1 Load instruction IR = Mem[PC] PC = PC + 1 Same as Load Copy instruction Cycle 2 R1 = RF[IR7..6] R2 = RF[IR5..4] Same as Load Cycle 3 MDR = mem[r2] Same as Load Cycle 4 RF[IR7..6] = MDR MEM[R1] = MDR Cycle 5 Cycle 6 Cycle 7 Page 11 of 23

12 [5 marks] (d) On the multi-cycle diagram, draw what changes are needed in the datapath to implement the copy instruction from Part c. Clearly indicate what part of the question (what cycle number) the modifications are for. An extra multicycle diagram has been provided for you; you must cross out the diagram that you do not wish to have marked. R1R2Load( 1(((((((((((0( AluOutWrite( Extra diagram for question 3d if needed. Cross out the diagram that you do not wish to have marked. Page 12 of 23

13 R1R2Load 1 0 AluOutWrite Page 13 of 23

14 4. Devices [12 marks] (a) I want to automate part of my home, so I am going to connect 16 power feeds for some appliances and lights in my home to a wireless-connected small processor which will listen to instructions over the internet and switch power circuits on and off appropriately. The processor has an asynchronous device connection with an 8-bit bidirectional data interface and a 16-bit address and I want to connect 16 relays through a 16-bit register (made up of 4 4-bit registers) that store the value when the Enable (E) input goes high to low. The unconnected parts are in the diagram below. Show the device connections to make this interface work. Acknowledgement (Ack), Master Enable (ME) have the same functionality as defined for the NIOS-II bus presented in lecture. You will only write to this device not read from it. Only this device is connected. Addresses from 0xF000 to 0xFFFF are free on the processor for this device. State any assumptions you feel are necessary. You are given two copies of the diagram. You must cross out the copy you do not want marked. wireless'link' Processor' D7 D0' 8' 16' A156A0' '' ME' '' Ack' '' R/~W' D3' D2' D1' D0' E' D3' D2' D1' D0' E' D3' D2' D1' D0' E' D3' D2' D1' D0' E' 46bit'Register' 46bit'Register' 46bit'Register' 46bit'Register' Drivers,'relays,'other'interface'hardware' Power'to'lights,'etc'connects'here' Note:'E'='Enable' Page 14 of 23

15 Extra diagram for Question 4a. Cross out the copy of the diagram that you do not want marked. wireless link Processor D7 D A15- A0 ME Ack R/~W D3 D2 D1 D0 E D3 D2 D1 D0 E D3 D2 D1 D0 E D3 D2 D1 D0 E 4- bit Register 4- bit Register 4- bit Register 4- bit Register Drivers, relays, other interface hardware Power to lights, etc connects here Note: E = Enable Page 15 of 23

16 [4 marks] (b) As a way for us to check your logic: For your specific interface, describe briefly how the programmer of the small processor would use the interface you prepared using specific processor addresses. DO NOT use the whole page; a few lines should be sufficient. stbio to address 0xF000 to write to device LSB stbio to address 0xF001 to write to device MSB Page 16 of 23

17 5. Interrupts You are going to write the interrupt handler for a NIOS-II in a system different from the DE2 Basic Computer used in the lab. There are only two devices connected to your NIOS-II that can raise interrupts, a UART and a VIDEO device. NEITHER DEVICE IS LIKE THE ONES ON THE DE2 THAT YOU PROGRAMMED IN THE LABS. Here is the information you need: UART device Has only a single byte buffer for receiving (not a FIFO queue like in the DE2). Operates at 1000 bytes per second. Interrupts on IRQ10 when the buffer is ready to be read. Buffer must be read before the next full byte of data (with control bits) is received, because this next byte will overwrite the buffer. You do not use the output of the UART. The data buffer is accessible at address 0x Interrupt is cleared when the data is read. The interrupt handler for the UART should read a single byte and do additional processing before returning to the interrupt routine. The additional processing is done by a call to subroutine void ManageByteIn(char CharInput) which you do not have to write but you do have to call; the subroutine handles saving and restoring all registers it uses. VIDEO device Must be handled on a high-priority basis. Interrupts on IRQ14 You must write zero to 0x to clear the interrupt. You do not need to write the body of the handler otherwise, but note where it would be. [16 marks] (a) Write the assembly-language interrupt handler for the NIOS-II to manage these devices. You do not have to write the setup routine. The VIDEO device must be able to interrupt the UART interrupt service routine. You can continue your code on the next page as needed. isr: rdctl et, ipending # first check if interrupt caused by video andi et, et, 0x4000 beq et, r0, check_uart # if not, check UART movia et, 0x # if yes, acknowledge the interrupt stwio r0, 0(et) # VIDEO BODY check_uart: rdctl et, ipending andi et, et, 0x400 bne et, r0, do_uart # if not uart, we are done isr_done: subi ea, ea, 4 eret # cont on next page Page 17 of 23

18 (extra space to continue 5a) do_uart: subi sp, sp, 16 stw r4, 0(sp) stw ra, 4(sp) stw ea, 8(sp) rdctl et, estatus stw et, 12(sp) movia r4, 0x ldwio r4, 0(r4) # ack interrupt ori et, et, 1 # enable interrupts wrctl ctl0, et call ManageByteIn wrtcl ctl0, r0 # disable interrupts ldw r4, 12(sp) wrctl estatus, r4 ldw r4, 0(sp) ldw ra, 4(sp) ldw ea, 8(sp) addi sp, sp, 16 br isr_done Page 18 of 23

19 [15 marks] 6. The data area of a NIOSII assembly program contains the following code: Camille:.string "Yonge" Cheng:.string "Bathurst" David:.string "Spadina" Prayosha:.string "College" Usman:.string "University".align 2 TeamStreets:.word Camille, Cheng, David, Prayosha, Usman (a).string,.align and.word are types of directives (b) If Camille is 0x1000, where does the string Bathurst start? 0x1006 (c) What does the.align 2 statement do? Ensures that following data is placed at the next address that is divisible by 4 (d) Assuming that all you know as a programmer is that TeamStreets has a word list of street names as shown above, and that you do not know what the streets are (because they might change if someone moves) i. Give the line(s) of assembly code that would put the fifth letter of the third street of TeamStreets (starting at 1) into r15. For example, for the data as it exists above, the fifth letter of the third street of TeamStreets would be i in Spadina. NOTE: The code should be very specific to get exactly that letter; it does not have to be and should not be code to get any letter from any street and can assume that street and letter are present in the data. movia r8, TeamStreets # r8 = TeamStreets ldw r8, 8(r8) # r8 = TeamStreets[2] ldb r15, 4(r8) # rr8 = TeamStreets[2][4] ii. If you were showing this code from part i in the C programming language, what might it look like? char **TeamStreets; result = TeamStreets[2][4]; Page 19 of 23

20 [15 marks] 7. Write a subroutine called hextoascii that converts a 4-bit hexadecimal value to the corresponding 7-bit ASCII code. For example, binary 0010 (hexadecimal digit 2) is converted to (ASCII code for 2). Another example, binary 1011 (hexadecimal digit B) is converted to (ASCII code for B) (see the attached ASCII table on next page for your reference). This subroutine has one input parameter in register r4. The least significant bits in register r4 specify a number, from 0 to 15. The values of the other bits in the input register must be ignored. One value is returned in register r2. The 7 least significant bits in register r2 must be an ASCII code corresponding to one of hex digits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F. All other bits in the register must be zero. The values in registers r2 through r15 may be changed. All other registers must have unchanged values when the subroutine returns. hextoascii: andi r4, r4, 0xF #ignore higher bits of r4 movi r2, 48 add r2, r2, r4 movi r8, 10 # for r4 < 10, r2 has correct value (48 + r4) blt r4, r8, done addi r2, r2, 7 #for r4 >= 10, adjust r2 done: ret Page 20 of 23

21 4/7/2014 ASCII - Wikipedia, the free encyclopedia Binary Oct Dec Hex Glyph ! " # $ % & ' ( ) A * B C, D E F / A : B ; C < D = E > F? Binary Oct Dec Hex Glyph A B C D E F G H I A J B K C L D M E N F O P Q R S T U V W X Y A Z B [ C \ D ] E ^ F _ Binary Oct Dec Hex Glyph ` a b c d e f g h i A j B k C l D m E n F o p q r s t u v w x y A z B { C D } E ~ 1/1 Page 21 of 23

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