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1 UNIVERSITY OF TORONTO FACULTY OF APPLIED SCIENCE AND ENGINEERING FINAL EXAMINATION, APRIL 2016 DURATION 2 and ½ hrs Second Year - ECE ECE243H1 S COMPUTER ORGANIZATION Exam Type: D Examiners P. Anderson, H. Timorabadi Instructions This is a type D exam. You are allowed to use any printed/hand-written material including your course notes. You may use a University-approved non-programmable calculator. You have 2.5 hours. Last Name (Print Clearly): First Name: Student Number: Question 1 /4 Question 2 /9 Question 3 /6 Question 4 /14 Question 5 /24 Question 6 /20 Question 7 /20 Question 8 /12 Total /109 General Instructions: State your assumptions. Show your work. Comment your code. Solutions that are judged significantly inefficient or are not legible will lose some marks. The exam is printed on two sides of the page. The last page and the back of this one are blank and can be used for answers or calculations. Make your answers clear. There are 8 questions and a total of 109 marks. There are 7 pieces of paper in the exam, this one included, printed both sides. The page numbering is to 14. ECE243 Computer Organization Pg 1 of 11 Spring 2016

2 Question 1 Basic Assembly [4 Marks] Assume we have defined the following:.equ D, 4.equ H, 0x8.data W:.word 0x1000 Will the instructions at the right compile? instruction addi r4, r3, r2 addi r4, r3, D ldw r2, r3(r4) ldw r2, H(r4) ldw r2, 0(W) stw D, 0(r2) yes/no? N Y N Y N N Question 2 -- Devices and interrupts [9 marks] Suppose you had the following program fragment that enables interrupts then goes into an infinite loop: 244: call ENABLE_INTERRUPTS_FOR_IO_DEVICES 248: movi r2, 4 24c: wrctl ienable, r2 Register Value or unknown 250: movi r2, 1 pc 0x20 254: wrctl status, r2 # Enable interrupts r0 0x00 258: LOOP: br LOOP # A loop r1 unknown 25c: movi r1, 0x : br LOOP 264:... r2 sp (r27) ea (r29) 0x01 unknown 0x25C Before starting the program you set a breakpoint at the exception address (0x20). The first interrupt comes after a couple of seconds of execution. What is the state of the system at the breakpoint? Fill in the boxes in the rightmost column of the first ra (r31) 0x248 status (ctl0) 0x00 estatus (ctl1) 0x01 ienable (ctl3) 0x04 ipending (ctl4) 0x04 table at the top of this question. Write unknown if there is not enough information to determine the value of a register. Notes: No issue if don t extend with zeros. Can do decimal or hex as long as the value is obvious ECE243 Computer Organization Pg 2 of 11 Spring 2016

3 Question 3 C To Assembly [6 Marks] Instances of the following structure is stored in the order given (ie there is no reordering of the structure by the compiler). Assume DogName is an ASCII zero-terminated string. struct doggies { int TagNum; char IsSpayed; char HasRabiesShot; int BreedCode; char DogName[10]; }; struct doggies Dog1 = {25,1,0,1023, Rover }; This structure is accessed in assembly language as follows: movia r10,dog1 ldbu r11,offset(r10) If r11 is loaded with a v, then what is the value of OFFSET? 14 Show your reasoning below for full marks. The struct has the following structure: TagNum offset 0 IsSpayed 4 HasRabiesShot 5 BreedCode 8 (padded for alignment) DogName 12 The third character of DogName is at offset 14 Question 4 Nios II assembly language programming [14 marks] Write a Nios II assembly language program that copies an 8-bit ASCII encoded string from label STR to label CPY. While copying, some characters are replaced by new characters according to a string at label MAPPING (see next page). The characters in string MAPPING are in pairs an example is shown. The first character is the original character that has to be replaced. The second character is a new replacement character. All strings are NULL-terminated (i.e. the last character is 0). The CPY has to end with zero (0) as well. You are given the.data section information on the next page, and the start of the.text section and need to complete the.text section. Your program should work with general values of MAPPING and STR inputs, not just those shown here as examples. Your implementation must have a subroutine called replacechar(c) that returns the replacement for character C if it is in the MAPPING list or returns the original character (C) if it is not in the MAPPING list. You do not need to caller-save or callee-save of any registers, but you must use Nios II conventions for the passed parameter(s) and returned values. This program requires no more than 20 additional lines of code. Plan first! ECE243 Computer Organization Pg 3 of 11 Spring 2016

4 Q4: CONTINUED.section.data MAPPING:.asciz "rrww" STR:.asciz "Here we go" CPY:.space (CPY-STR),0xFF #start with all = 0xFF.section.text.global start start: movia r15, STR movia r16, CPY LOOP: ldbu r4,0(r15) #get character from input string call replacechar stb r2,0(r16) #store translated char in output beq r2,r0,done #zero means end of string addi r15,r15,1 #to next character addi r16,r16,1 br LOOP DONE: br DONE replacechar: #input char in r4, translated char out in r2 movia r11,mapping #translation table (can use any reg) mov r2,r4 #default return value rc1: ldbu r10,0(r11) #get char to translate (again, any reg) beq r10,r0,rc3 #exit on zero at end of table beq r10,r4,rc2 #br if found input char in table addi r11, r11,2 #to next place in table br rc1 #back to try next in table rc2: ldbu r2,1(r11) #make translation rc3: ret Notes: You can do this in at least one fewer instructions. ECE243 Computer Organization Pg 4 of 11 Spring 2016

5 Question 5 -- Caches [24 Marks] a) [12 marks] You have a 1 MB cache with 256 byte blocks and a 32-bit address. i. Fill in all the cells with a question mark in the following table showing the number of bits of the address used in cache access for three different organizations. Fill the blank cell in the first column with the correct name of the third organizational method and the blank cell in the top row with the name of the third portion of the address. Organization Method Direct 2-way SA Fully Associative Tag Set/Block Offset? 12? 12? 8? 13? 11? 8? 24 0? 8 ii. [Same memory system as for part i] Complete the following hit/miss table for two different organizations. Note that you have to fill in addresses in some cases. Where there are more than one correct answer, provide only one of these. Use LRU replacement where required. Two columns are available for your calculations. Assume the cache is empty at the start. Address Direct (H/M) 2-Way SA (H/M) Cache Blocks used Set Tag (direct) (All numbers hex) Cache Blocks used Set Tag* (2W) 0x M M : x M M : x M M : x H H hit set 100 hit 100:1 0x M M : x H H hit set 000 hit 000:1 0x H H hit set 000 hit 000:1 0x M H any from (set=0,tag not 020) or (set=100, tag not 010) 0x M M any except ((set 0,tag 000) or (set 0,tag 020) or (set 100,tag 000) or (set 100,tag 010)) 0x H H See notes * Note that the tag for 2W is actually 13 bits, but we wrote only the upper 12 bits in hex for clarity (LSB is always 0 because we chose nice addresses). The block is designated s:b where s is the set and b the block in the set. Notes for last row: Easiest will be last input repeated, next easiest will be input from before that, provided the last doesn t use the same cache block. ECE243 Computer Organization Pg 5 of 11 Spring 2016

6 b. [12 marks] A cache block size is 64 bytes organized as 4-byte words. The cache takes 5 ns to resolve a hit and return cached data. On a miss, the new block must be completely loaded, then there is a further 5 ns to return the addressed data. To fetch each word (4 bytes) from main memory takes 100 ns for both requests from the cache or from the processor if there was no cache. Do not concern yourself with writes. What minimum hit rate is necessary in order to justify having a cache by an overall average increase in memory system speed? If no cache every fetch costs 100 ns If there is cache: a. A hit costs 5 ns b. A miss costs 100 ns for every word of the cache block that must be loaded, plus 5 ns Considering b: There are 64/4=16 words, so it costs 16*100 ns to load the block. The cache is justified for a cache hit rate of x if x * 5ns + (1-x)*(5ns+1600ns+5ns) < 100ns or x > 1510/1605 =.94 (or 94%) ECE243 Computer Organization Pg 6 of 11 Spring 2016

7 Question 6 -- Processor Implementation [20 Marks] On the following pages are two copies of diagrams of a multiple cycle machine that was studied in class. You want to implement the following instruction: Sumall which does R1 RF[0]+RF[1]+RF[2]+RF[3] Note: Ignore the N and Z flags. a) On one of the diagrams show the datapath alterations to make this instruction possible. If you make a significant mistake that makes your intent unclear, draw an X through that diagram and use the other one. b) Add to the control flow diagram directly below the operations performed at each cycle to make this instruction work. You can use the rightmost columns for notes so your final version is neater. The sequences for some instructions have been omitted to save space. Note: Your solution should not exceed 11 cycles, and can take as few as 7. FILL THIS OUT FOR PART b. Add, Sub, Nand Ori Load Sumall for notes for notes 1 IR = [PC] PC = PC OpA = RF[IR7,IR6] OpB = RF[IR5,IR4] 3 ALUout = OpA op R2 OPA = RF[1] MDR = mem[r2] OpA = RF[1] OpB = RF[0] 4 RF[IR7,IR6] = ALUout ALUout = OpA RF[IR7,IR6] = MDR OpA = RF[2] ALUout = OpA+OpB OR Imm5 5 X RF[1] = ALUout X OpA = RF[3] ALUout = OpA+ALUout 6 X X X ALUout = OpA+ALUout 7 X X X RF[1] = ALUout 8 X X X 9 X X X 10 X X X 11 X X X ECE243 Computer Organization Pg 7 of 11 Spring 2016

8 2 3 0 Summary of changes: 1. Multiplexor in front of reg2 which selects 0 as well as IR5-. New control input OpBSel. 2. Additional inputs to multiplexor in front of reg1 to select 2 and 3 as well as 1 and IR6-7. OpASel would be 2 bits. 3. Additional input to multiplexor in front of lower ALU input to select ALU value. No change in control required. ECE243 Computer Organization Pg 8 of 11 Spring 2016

9 Question 7 -- Building Memories and Bus Interfaces [20 Marks] You have a bunch of memory chips, a pushbutton switch, and a buzzer that is turned on (off) by writing a 1 (0) to a single data line with the enable high. You also have a processor that only reads, writes and uses 16-bit words (not bytes; the address space is word-addressable). You will use these to build a system for a friend with interface shown below, an 8Kx16bit memory, the switch and the buzzer. You determine that the way to save hardware is to configure it with the following memory map: Item Memory Address Range Switch 0x0000-0x7FFF (on load into processor [read]) Buzzer 0x0000-0x7FFF (on store from processor [write]) Memory 0x8000-0xFFFF (loads and stores to/from processor [read/write]) What this means, for example, is that you can read the value from the switch using an address of 0x0000 or 0x0001 or 0x0002 or or 0x7FFF since there is only a single switch being accessed and it can be reached at these duplicate word addresses. a) [12 marks] Draw the bus interface circuitry for this system. You can NOT use a match circuit, but must use only tri-state buffers and AND, OR and NOT gates which may have inverted inputs. Minimal circuits receive full marks. Note that all the memory is shown as a black box. Label each line. Make your intent clear. A0-A15 ME ACK R/~W D0-D15 A0-A? R/~W EN 8K by 16bit memory unit D0-D15 Switch Enable Buzzer On/~Off ECE243 Computer Organization Pg 9 of 11 Spring 2016

10 b) [8 marks] Show how the memory unit would be implemented using 4K by 8 bit memory chips, with the construction shown at the right. A0-A11 EN D0-D7 R/~W memory unit interface A0-A? R/~W EN D0-D15 Put your array of memory chips here and show their interconnections to the memory unit interface at the top of the page ECE243 Computer Organization Pg 10 of 11 Spring 2016

11 Question 8 - Pipelining [12 marks] a) For the instruction sequence shown, complete the cycle by cycle behaviour for the pipelined structure shown above using F, D and E. Show all cycles up to 12 (instructions may repeat). The first instruction (instr ID=A) is done for you. instr ID Cycle A movi r10,2 F D E B LOOP: add r11,r11,r9 F D E F D E C addi r11,r11,5 F - D E F - D addi r10,r10,-1 F D E E add r12,r6,r4 F D E F bne r10,r0,loop F D E G add r6,r7,r8 H addi r8,r8,1 I addi r7,r7,5 b) Show how you can rearrange the instructions in the program to eliminate the data hazard. Use the instruction IDs at the left to show the sequence. For example, the present order of instructions is A B C D E F G H I A B D C E F G H I c) Give an alternate set of instructions that would do the same computations, but would eliminate the control hazard. Full marks if your solution takes no longer (in numbers of instructions executed) than the given instructions. Use the same method to show the sequence as in part b, extending the method if you need to. mov r10,r0 then: B C E B C E G H I Can further reduce by combining the two C s into addi r5,r5,10 and recognizing that the second E makes no change in the end state. ECE243 Computer Organization Pg 11 of 11 Spring 2016