1. Number Conversions [8 marks]
|
|
- Jacob Barker
- 5 years ago
- Views:
Transcription
1 1. Number Conversions [8 marks] a. convert the decimal number 42 to a 16-bit signed integer in binary 0b b. convert the 8-bit number 0x42 to a 16-bit signed integer in binary 0b c. convert the signed 8-bit number 0x5A to a 32-bit signed integer in hexadecimal 0x A d. convert the signed 7-bit number 0x5A to a 32-bit signed integer in hexadecimal 0xFFFFFFDA e. convert -2^16 to a 32-bit signed integer in hexadecimal 0xFFFF0000 f. encode 2.25 in 32-bit floating point (IEEE 754), show the result in binary. Show how each of the parts of the floating point number is found. Sign: + => 0 Integer part: 2 = 0b010 Decimal part:.25 = 0b Mantissa = 0b thus we use 0b in the representation Exponent = 1 thus we use =128 = in the representation Answer is thus 0b Page 1 of 9 Midterm ECE243 March 2016
2 Instructions [14 marks] Operations [8 marks] r2 0x r3 r4 r5 0x x xF0F0F0F0 Example solutions: movi r2,0 ans: r2 = 0x Address 0x1000 0x1004 0x1008 Data Word 0x x x stw r0,0(r0) ans: mem[0] = 0x Indicate the new 32-bit value and register or memory location that changes after executing the following instructions, using the format from the example. Use the same initial state above for each part. Note that memory is shown as a set of words, so you do not need to consider endianness in this question. a) add r4, r3, r2 r4=0x c b) slli r4, r3, 4 r4=0x c) ldw r3, 4(r2) r3=0x d) stw r3, 0(r2) mem[1004]=0x e) mov r4, r3 r4=0x f) movi r2, -1 r2=0xffffffff g) and r2, r2, r5 r2=0x h) or r2, r2, r5 r2=0xf0f0f0f4 Page 2 of 9 Midterm ECE243 March 2016
3 2.2 Sign extension and endianess [6 marks] Show the result of the last instruction in each sequence for Nios II (little endian) given the following initial state of memory. Sometimes it might be changes in memory; sometimes it might be changes in register contents. Use the same initial state for each part. Use the notation rx = 0x######## for register changes or mem[address] = 0x## for each byte in memory that gets updated (you may need multiple lines). Example: mov r2,r0 Answer: mem[0] = 0x00 stw r2,0(r0) mem[1] = 0x00 mem[2] = 0x00 mem[3] = 0x00 Address 0x0 0x1 Data Byte 0x0a 0x1b c) movi r2, 4 ldh r3, 2(r2) r3=0xffffd7c6 0x2 0x3 0x4 0x5 0x6 0x7 0x2c 0x3d 0xa4 0xb5 0xc6 0xd7 a) movi r2, 0 ldw r3, 0(r2) r3=0x3d2c1b0a b) movi r2, 4 ldhu r3, 0(r2) d) movi r2, 2 ldbu r3, 3(r2) r3=0x000000b5 e) movi r2, 3 ldb r3, 0(r2) r3=0x d f) movi r2, 2 movi r3, -2 sth r3, 0(r2) mem[0x02]=0xfe mem[0x03]=0xff r3=0x0000b5a4 Page 3 of 9 Midterm ECE243 March 2016
4 3. Calling conventions [6 marks] You are writing an assembly subroutine foo, which must interface with functions written in C: foo is called by main, and foo calls bar1 and bar2. All of the code for foo is provided below. For each push and pop, circle only the registers that need to be saved (pushed) and restored (popped). Recall caller-saved and callee-saved registers. Use as few pushes and pops as possible maintaining convention: Do not save any registers that you know will not be overwritten or will not be read later; you will lose marks otherwise. foo: push sp, ra, r2, r4, r5, r12, r13, r14, r15, r16, r17 movia r12, 0x10000 # memory address 1 movia r13, 0x20000 # memory address 2 movi r14, 0 # accumulator; return value movi r15, 0xFF # bit mask 1 movi r16, 0xF # bit mask 2 movi r17, 3 # scaling factor and r4, r4, r15 ldw r5, 0(r12) Example If you think r2, r5 and r15 need to be saved, you would circle those like so: push sp, ra, r2, r4, r5, r12, r13, r14, r15, r16, r17 push sp, ra, r2, r4, r5, r12, r13, r14, r15, r16, r17 call bar1 # arguments r4 and r5; returns r2 pop sp, ra, r2, r4, r5, r12, r13, r14, r15, r16, r17 stw r2, 4(r12) add r14, r14, r2 and r4, r4, r16 ldw r5, 0(r13) push sp, ra, r2, r4, r5, r12, r13, r14, r15, r16, r17 call bar2 # arguments r4 and r5; returns r2 pop sp, ra, r2, r4, r5, r12, r13, r14, r15, r16, r17 stw r2, 4(r13) add r14, r14, r2 mul r14, r14, r17 and r14, r14, r16 mov r2, r14 pop sp, ra, r2, r4, r5, r12, r13, r14, r15, r16, r17 ret Page 4 of 9 Midterm ECE243 March 2016
5 4. Understanding assembly [11 marks] a. [5 marks] Write the equivalent C code for this subroutine. Note that you may be able to do parts b and/or c even if you don t get this part. foo: bar: bne r0, r4, bar movi r2, 1 ret # part c addi sp, sp, -8 stw r4, 0(sp) stw ra, 4(sp) addi r4, r4, -1 call foo ldw r4, 0(sp) ldw ra, 4(sp) mul r2, r2, r4 addi sp, sp, 8 ret integer foo(integer n) { if (n == 0) return 1; else return n*foo(n-1); } b. [1 mark] What well-known function does this subroutine implement? n! or n factorial Page 5 of 9 Midterm ECE243 March 2016
6 c. [5 marks] Assume the subroutine on the last page is called like this: main: movia sp, 0x movi r4, 4 call foo Draw the contents of the stack (addresses and word data) used by foo and its descendants immediately before executing the ret instruction with the comment part c (the third instruction of the subroutine). Also indicate the current value of the stack pointer. Assume main = 0x1000 and foo = 0x2000. sp value = 03FFFFE0 Memory Address (words) Data 03FFFFE0 1 03FFFFE4 0x FFFFE8 2 03FFFEC 0x FFFFF0 3 03FFFFF4 0x FFFFFF8 4 03FFFFFC 0x Page 6 of 9 Midterm ECE243 March 2016
7 5. New device [12 marks] Below is a new device for the Nios II, a UART serial device, but different than the ones you have been using. For this one you need to set the bit rate, the data size for each transmission (in bits) and the number of stop bits, and you can set parity. There is no FIFO with the input or with the output, only simple singlemessage buffers. Note: bit rate as used here is equivalent to baud rate or bits of information over the wire (including all the extra bits that surround the actual message) Produce commented code that does the following. Assume the processor clock rate is 1 MHz. a. i) Set the bit rate to 2000 bits per second ii) Start the receiver and transmitter with even parity, normal number of stop bits, 8 bits per message (data sent/received) and with interrupts enabled # 2000 bits/sec => /2000 = 500 bits/sec movia r10,0xff2f0000 #set base address (used in all parts of the answer) movi r11,500 #set baud rate to 500 clocks/bit stwio r11,8(r10) #end of answer to i part movi r11,0b #set control bits for operation as requested stwio r11,12(r10) #end of answer to ii part Page 7 of 9 Midterm ECE243 March 2016
8 b. Write the additional lines of code that would check to see if a character had been input, and that will read the character if into r10 if it was ready. Assume the initialization specified in part a, except with interrupts disabled. You need only write the lines that actually answer this question and not any context, such as putting it into a subroutine. CheckRead: #assume r10 still set to base address ldw r11,4(r10) #get status information andi r11,r11,0x01 #check read bit (note: could check for errors here, wasn t asked for) beq CheckReadDone #br if no character available ldw r11,0(r10) #get read character # one would process the read character in r11 here CheckReadDone: #done the read check c. Write the initialization code that, in addition to the code in part a, would be required to make interrupts active for this device on this processor. Assume there are no other interrupting devices. The interrupt should be fully active on the processor after the code from part a and the code from part c are executed. #there are 2 more steps to do, since the interrupts at the device were already enabled movi r11,0x0400 #set interrupt enable #10 wrctl ienable,r11 movi r11,0x01 #set the PIE bit for global interrupt enable wrctl status,r11 Page 8 of 9 Midterm ECE243 March 2016
9 6. Write a subroutine [18 marks] You have a linked list with each node implemented as follows: struct node { int data; struct node* next; }; The following function allows the user to insert a new node after a node of given index (head node has an index of 0) in the linked list. The insertion function is implemented as follows: void insert(int insert_after, struct node *newnode, struct node *head)//the data for newnode is already set { struct node *prev = head; // You can assume insert_after will always lie within the linked list for (int index = 0; index < insert_after; index++) { prev = prev->next; } struct node *before = prev; struct node *after = prev->next; newnode->next = after; before->next = newnode; } return; You are to write the insertion function in Nios II assembly language. Be sure to follow the calling convention of the Nios II ABI. #note: on call r4=insert_after (# of nodes), r5=*newnode, r6=*head insert: beq r4,r0,atinsertposition addi r4,r4,-1 ldw r6,4(r6) #go to next node br insert #continue until at insertion point atinsertposition: ldw r4,4(r6) #pick up pointer stw r5,4(r6) #replace with pointer to new element stw r4,4(r5) #point new element with next in line ret #done # note that this used parameter registers to avoid having to save registers on the stack. # any callee-save registers used must be saved on the stack Page 9 of 9 Midterm ECE243 March 2016
Last Name (in case pages get detached): UNIVERSITY OF TORONTO FACULTY OF APPLIED SCIENCE AND ENGINEERING MIDTERM EXAMINATION, MARCH 2011
Page 1 of 13 UNIVERSITY OF TORONTO FACULTY OF APPLIED SCIENCE AND ENGINEERING MIDTERM EXAMINATION, MARCH 2011 ECE243H1 S COMPUTER ORGANIZATION Exam Type: D Duration: 2 Hours Prof.s Anderson, Enright Jerger,
More information8. Instruction Set Reference
8. Instruction Set Reference NII51017-7.1.0 Introduction This section introduces the Nios II instruction-word format and provides a detailed reference of the Nios II instruction set. This chapter contains
More informationStudent # (use if pages get separated)
UNIVERSITY OF TORONTO FACULTY OF APPLIED SCIENCE AND ENGINEERING FINAL EXAMINATION, APRIL 2016 DURATION 2 and ½ hrs Second Year - ECE ECE243H1 S COMPUTER ORGANIZATION Exam Type: D Examiners P. Anderson,
More informationUniversity of Toronto Faculty of Applied Science and Engineering
Print: First Name:............................. Last Name:............................. Student Number:............................................... University of Toronto Faculty of Applied Science and
More informationEN164: Design of Computing Systems Topic 03: Instruction Set Architecture Design
EN164: Design of Computing Systems Topic 03: Instruction Set Architecture Design Professor Sherief Reda http://scale.engin.brown.edu Electrical Sciences and Computer Engineering School of Engineering Brown
More information8. Instruction Set Reference
8. NII51017-10.0.0 Introduction This section introduces the Nios II instruction word format and provides a detailed reference of the Nios II instruction set. This chapter contains the following sections:
More informationLast Name (in case pages get detached): UNIVERSITY OF TORONTO FACULTY OF APPLIED SCIENCE AND ENGINEERING FINAL EXAMINATION, APRIL 2011
Page 1 of 17 UNIVERSITY OF TORONTO FACULTY OF APPLIED SCIENCE AND ENGINEERING FINAL EXAMINATION, APRIL 2011 ECE243H1 S COMPUTER ORGANIZATION Exam Type: D Duration: 2.5 Hours Prof.s Anderson, Enright Jerger,
More informationENGN1640: Design of Computing Systems Topic 03: Instruction Set Architecture Design
ENGN1640: Design of Computing Systems Topic 03: Instruction Set Architecture Design Professor Sherief Reda http://scale.engin.brown.edu School of Engineering Brown University Spring 2014 Sources: Computer
More informationUniversity of Toronto Faculty of Applied Science and Engineering Department of Electrical and Computer Engineering Final Examination
University of Toronto Faculty of Applied Science and Engineering Department of Electrical and Computer Engineering Final Examination ECE 253F - Digital and Computer Systems Friday December 10, 2010 Duration:
More informationChapter 2A Instructions: Language of the Computer
Chapter 2A Instructions: Language of the Computer Copyright 2009 Elsevier, Inc. All rights reserved. Instruction Set The repertoire of instructions of a computer Different computers have different instruction
More informationEN164: Design of Computing Systems Lecture 11: Processor / ISA 4
EN164: Design of Computing Systems Lecture 11: Processor / ISA 4 Professor Sherief Reda http://scale.engin.brown.edu Electrical Sciences and Computer Engineering School of Engineering Brown University
More informationDebugging of Application Programs on Altera s DE-Series Boards. 1 Introduction
Debugging of Application Programs on Altera s DE-Series Boards 1 Introduction This tutorial presents some basic concepts that can be helpful in debugging of application programs written in the Nios II
More information231 Spring Final Exam Name:
231 Spring 2010 -- Final Exam Name: No calculators. Matching. Indicate the letter of the best description. (1 pt. each) 1. address 2. object code 3. condition code 4. byte 5. ASCII 6. local variable 7..global
More information8. Instruction Set Reference
8. May 2011 NII51017-11.0.0 NII51017-11.0.0 This section introduces the Nios II instruction word format and provides a detailed reference of the Nios II instruction set. This chapter contains the following
More informationDo-While Example. In C++ In assembly language. do { z--; while (a == b); z = b; loop: addi $s2, $s2, -1 beq $s0, $s1, loop or $s2, $s1, $zero
Do-While Example In C++ do { z--; while (a == b); z = b; In assembly language loop: addi $s2, $s2, -1 beq $s0, $s1, loop or $s2, $s1, $zero 25 Comparisons Set on less than (slt) compares its source registers
More informationMIPS Functions and Instruction Formats
MIPS Functions and Instruction Formats 1 The Contract: The MIPS Calling Convention You write functions, your compiler writes functions, other compilers write functions And all your functions call other
More information2) Using the same instruction set for the TinyProc2, convert the following hex values to assembly language: x0f
CS2 Fall 28 Exam 2 Name: ) The Logisim TinyProc2 has four instructions, each using 8 bits. The instruction format is DR SR SR2 OpCode with OpCodes of for add, for subtract, and for multiply. Load Immediate
More informationI expect you to understand everything discussed prior to this page. In particular:
A NOTE TO 259 STUDENTS: Interrupts involve a lot of details. The details presented after this page provide further background on exactly what happens at the CPU logic and assembly code levels. This may
More informationCSCI 402: Computer Architectures. Instructions: Language of the Computer (3) Fengguang Song Department of Computer & Information Science IUPUI.
CSCI 402: Computer Architectures Instructions: Language of the Computer (3) Fengguang Song Department of Computer & Information Science IUPUI Recall Big endian, little endian Memory alignment Unsigned
More informationCSE 351 Midterm - Winter 2017
CSE 351 Midterm - Winter 2017 February 08, 2017 Please read through the entire examination first, and make sure you write your name and NetID on all pages! We designed this exam so that it can be completed
More information1 Address space with memory mapped devices
1 Address space with memory mapped devices In systems with memory mapped devices, the devices appear as regions of memory. The addresses that these devices occupy are determined by the system designer.
More informationBasic Computer System for the Altera DE1 Board. 1 Introduction. 2 DE1 Basic Computer Contents. 2.1 Nios II Processor.
Basic Computer System for the Altera DE1 Board For Quartus II 8 1 Introduction This document describes a simple computer system that can be implemented on the Altera DE1 development and education board.
More informationFinal Exam. 11 May 2018, 120 minutes, 26 questions, 100 points
Name: CS520 Final Exam 11 May 2018, 120 minutes, 26 questions, 100 points The exam is closed book and notes. Please keep all electronic devices turned off and out of reach. Note that a question may require
More informationEE 361 University of Hawaii Fall
C functions Road Map Computation flow Implementation using MIPS instructions Useful new instructions Addressing modes Stack data structure 1 EE 361 University of Hawaii Implementation of C functions and
More informationDE2-115 Computer System. 1 Introduction. 2 DE2-115 Computer Contents. 2.1 Nios II Processor. For Quartus Prime 16.1
DE2-115 Computer System For Quartus Prime 16.1 1 Introduction This document describes a computer system that can be implemented on the Intel DE2-115 development and education board. This system, called
More informationAssembly labs start this week. Don t forget to submit your code at the end of your lab section. Download MARS4_5.jar to your lab PC or laptop.
CSC258 Week 10 Logistics Assembly labs start this week. Don t forget to submit your code at the end of your lab section. Download MARS4_5.jar to your lab PC or laptop. Quiz review A word-addressable RAM
More information1 Number Representation(10 points)
Name: Sp15 Midterm Q1 1 Number Representation(10 points) 1 NUMBER REPRESENTATION(10 POINTS) Let x=0xe and y=0x7 be integers stored on a machine with a word size of 4bits. Show your work with the following
More informationFinal Exam. 12 December 2018, 120 minutes, 26 questions, 100 points
Name: CS520 Final Exam 12 December 2018, 120 minutes, 26 questions, 100 points The exam is closed book and notes. Please keep all electronic devices turned off and out of reach. Note that a question may
More informationCSE Lecture In Class Example Handout
CSE 30321 Lecture 07-09 In Class Example Handout Part A: A Simple, MIPS-based Procedure: Swap Procedure Example: Let s write the MIPS code for the following statement (and function call): if (A[i] > A
More informationSubroutines. int main() { int i, j; i = 5; j = celtokel(i); i = j; return 0;}
Subroutines Also called procedures or functions Example C code: int main() { int i, j; i = 5; j = celtokel(i); i = j; return 0;} // subroutine converts Celsius to kelvin int celtokel(int i) { return (i
More informationMachine Language Instructions Introduction. Instructions Words of a language understood by machine. Instruction set Vocabulary of the machine
Machine Language Instructions Introduction Instructions Words of a language understood by machine Instruction set Vocabulary of the machine Current goal: to relate a high level language to instruction
More informationBasic Computer System for the Altera DE0-Nano Board. 1 Introduction. 2 DE0-Nano Basic Computer Contents. 2.1 Nios II Processor. For Quartus II 13.
Basic Computer System for the Altera DE0-Nano Board For Quartus II 13.0 1 Introduction This document describes a simple computer system that can be implemented on the Altera DE0-Nano development and education
More informationCENG3420 Lecture 03 Review
CENG3420 Lecture 03 Review Bei Yu byu@cse.cuhk.edu.hk 2017 Spring 1 / 38 CISC vs. RISC Complex Instruction Set Computer (CISC) Lots of instructions of variable size, very memory optimal, typically less
More informationLecture V Toy Hardware and Operating System
2. THE Machine Lecture V Page 1 Lecture V Toy Hardware and Operating System 1. Introduction For use in our OS projects, we introduce THE Machine where THE is an acronym 1 for Toy HardwarE. We also introduce
More informationCSCE 5610: Computer Architecture
HW #1 1.3, 1.5, 1.9, 1.12 Due: Sept 12, 2018 Review: Execution time of a program Arithmetic Average, Weighted Arithmetic Average Geometric Mean Benchmarks, kernels and synthetic benchmarks Computing CPI
More informationStack Frames. September 2, Indiana University. Geoffrey Brown, Bryce Himebaugh 2015 September 2, / 15
Stack Frames Geoffrey Brown Bryce Himebaugh Indiana University September 2, 2016 Geoffrey Brown, Bryce Himebaugh 2015 September 2, 2016 1 / 15 Outline Preserving Registers Saving and Restoring Registers
More informationChapter 2. Computer Abstractions and Technology. Lesson 4: MIPS (cont )
Chapter 2 Computer Abstractions and Technology Lesson 4: MIPS (cont ) Logical Operations Instructions for bitwise manipulation Operation C Java MIPS Shift left >>> srl Bitwise
More informationECE232: Hardware Organization and Design
ECE232: Hardware Organization and Design Lecture 4: Logic Operations and Introduction to Conditionals Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Overview Previously examined
More informationDetailed Nios II Exception Process
Detailed Nios II Exception Process When an exception is triggered, the CPU does the following steps automatically: 1. Copy the contents of status to estatus to save pre-exception state 2. Clear (0) PIE
More informationCompiling Code, Procedures and Stacks
Compiling Code, Procedures and Stacks L03-1 RISC-V Recap Computational Instructions executed by ALU Register-Register: op dest, src1, src2 Register-Immediate: op dest, src1, const Control flow instructions
More informationCOMP 303 Computer Architecture Lecture 3. Comp 303 Computer Architecture
COMP 303 Computer Architecture Lecture 3 Comp 303 Computer Architecture 1 Supporting procedures in computer hardware The execution of a procedure Place parameters in a place where the procedure can access
More informationECE 331 Hardware Organization and Design. Professor Jay Taneja UMass ECE - Discussion 5 2/22/2018
ECE 331 Hardware Organization and Design Professor Jay Taneja UMass ECE - jtaneja@umass.edu Discussion 5 2/22/2018 Today s Discussion Topics Program Concepts Floating Point Floating Point Conversion Floating
More informationComputer Architecture and System Software Lecture 06: Assembly Language Programming
Computer Architecture and System Software Lecture 06: Assembly Language Programming Instructor: Rob Bergen Applied Computer Science University of Winnipeg Announcements Assignment 3 due thursday Midterm
More informationCS , Fall 2002 Exam 1
Andrew login ID: Full Name: CS 15-213, Fall 2002 Exam 1 October 8, 2002 Instructions: Make sure that your exam is not missing any sheets, then write your full name and Andrew login ID on the front. Write
More informationLecture 2. Instructions: Language of the Computer (Chapter 2 of the textbook)
Lecture 2 Instructions: Language of the Computer (Chapter 2 of the textbook) Instructions: tell computers what to do Chapter 2 Instructions: Language of the Computer 2 Introduction Chapter 2.1 Chapter
More informationLecture 5: Procedure Calls
Lecture 5: Procedure Calls Today s topics: Procedure calls and register saving conventions 1 Example Convert to assembly: while (save[i] == k) i += 1; i and k are in $s3 and $s5 and base of array save[]
More informationCENG3420 Computer Organization and Design Lab 1-2: System calls and recursions
CENG3420 Computer Organization and Design Lab 1-2: System calls and recursions Wen Zong Department of Computer Science and Engineering The Chinese University of Hong Kong wzong@cse.cuhk.edu.hk Overview
More informationMIPS%Assembly% E155%
MIPS%Assembly% E155% Outline MIPS Architecture ISA Instruction types Machine codes Procedure call Stack 2 The MIPS Register Set Name Register Number Usage $0 0 the constant value 0 $at 1 assembler temporary
More informationLecture 5. Announcements: Today: Finish up functions in MIPS
Lecture 5 Announcements: Today: Finish up functions in MIPS 1 Control flow in C Invoking a function changes the control flow of a program twice. 1. Calling the function 2. Returning from the function In
More informationcomp 180 Lecture 10 Outline of Lecture Procedure calls Saving and restoring registers Summary of MIPS instructions
Outline of Lecture Procedure calls Saving and restoring registers Summary of MIPS instructions Procedure Calls A procedure of a subroutine is like an agent which needs certain information to perform a
More informationECE 331 Hardware Organization and Design. Professor Jay Taneja UMass ECE - Discussion 3 2/8/2018
ECE 331 Hardware Organization and Design Professor Jay Taneja UMass ECE - jtaneja@umass.edu Discussion 3 2/8/2018 Study Jams Leader: Chris Bartoli Tuesday 5:30-6:45pm Elab 325 Wednesday 8:30-9:45pm Elab
More informationece4750-tinyrv-isa.txt
========================================================================== Tiny RISC-V Instruction Set Architecture ========================================================================== # Author :
More informationCSIS1120A. 10. Instruction Set & Addressing Mode. CSIS1120A 10. Instruction Set & Addressing Mode 1
CSIS1120A 10. Instruction Set & Addressing Mode CSIS1120A 10. Instruction Set & Addressing Mode 1 Elements of a Machine Instruction Operation Code specifies the operation to be performed, e.g. ADD, SUB
More informationCS356: Discussion #6 Assembly Procedures and Arrays. Marco Paolieri
CS356: Discussion #6 Assembly Procedures and Arrays Marco Paolieri (paolieri@usc.edu) Procedures Functions are a key abstraction in software They break down a problem into subproblems. Reusable functionality:
More informationENGN1640: Design of Computing Systems Topic 03: Instruction Set Architecture Design
ENGN1640: Design of Computing Systems Topic 03: Instruction Set Architecture Design Professor Sherief Reda http://scale.engin.brown.edu School of Engineering Brown University Spring 2016 1 ISA is the HW/SW
More informationNET3001. Advanced Assembly
NET3001 Advanced Assembly Arrays and Indexing supposed we have an array of 16 bytes at 0x0800.0100 write a program that determines if the array contains the byte '0x12' set r0=1 if the byte is found plan:
More informationComputer Organization and Components
2 Course Structure Computer Organization and Components Module 4: Memory Hierarchy Module 1: Logic Design IS1500, fall 2014 Lecture 4: and F1 DC Ö1 F2 DC Ö2 F7b Lab: dicom F8 Module 2: C and Associate
More informationECE 473 Computer Architecture and Organization Lab 4: MIPS Assembly Programming Due: Wednesday, Oct. 19, 2011 (30 points)
ECE 473 Computer Architecture and Organization Lab 4: MIPS Assembly Programming Due: Wednesday, Oct. 19, 2011 (30 points) Objectives: Get familiar with MIPS instructions Assemble, execute and debug MIPS
More informationECE260: Fundamentals of Computer Engineering
Accessing and Addressing Memory James Moscola Dept. of Engineering & Computer Science York College of Pennsylvania Based on Computer Organization and Design, 5th Edition by Patterson & Hennessy American
More informationData Structure Layout. In HERA/Assembly
Data Structure Layout In HERA/Assembly Today, we re going to build some data structures in HERA First, a note on memory Registers are very fast RAM is relatively slow We use a cache to sit between them
More informationLecture 5: Procedure Calls
Lecture 5: Procedure Calls Today s topics: Memory layout, numbers, control instructions Procedure calls 1 Memory Organization The space allocated on stack by a procedure is termed the activation record
More information1 /18 2 /16 3 /18 4 /26 5 /22
M A S S A C H U S E T T S I N S T I T U T E O F T E C H N O L O G Y DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE 6.004 Computation Structures Fall 2018 Quiz #2 1 /18 2 /16 3 /18 4 /26 5 /22
More informationCS 316: Procedure Calls/Pipelining
CS 316: Procedure Calls/Pipelining Kavita Bala Fall 2007 Computer Science Cornell University Announcements PA 3 IS out today Lectures on it this Fri and next Tue/Thu Due on the Friday after Fall break
More informationToday s Menu. >Use the Internal Register(s) >Use the Program Memory Space >Use the Stack >Use global memory
Today s Menu Methods >Use the Internal Register(s) >Use the Program Memory Space >Use the Stack >Use global memory Look into my See examples on web-site: ParamPassing*asm and see Methods in Software and
More informationCS401 Assembly Language Solved MCQS From Midterm Papers
CS401 Assembly Language Solved MCQS From Midterm Papers May 14,2011 MC100401285 Moaaz.pk@gmail.com MC100401285@gmail.com PSMD01(IEMS) Question No:1 ( Marks: 1 ) - Please choose one The first instruction
More informationCprE 281: Digital Logic
CprE 281: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Floating Point Numbers CprE 281: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev
More informationProgramming the ARM. Computer Design 2002, Lecture 4. Robert Mullins
Programming the ARM Computer Design 2002, Lecture 4 Robert Mullins 2 Quick Recap The Control Flow Model Ordered list of instructions, fetch/execute, PC Instruction Set Architectures Types of internal storage
More informationGrading: 3 pts each part. If answer is correct but uses more instructions, 1 pt off. Wrong answer 3pts off.
Department of Electrical and Computer Engineering University of Wisconsin Madison ECE 552 Introductions to Computer Architecture Homework #2 (Suggested Solution) 1. (10 points) MIPS and C program translations
More informationFirst Semester Examination Introduction to Computer Systems (COMP2300/COMP6300)
First Semester Examination 2011 Introduction to Computer Systems (COMP2300/COMP6300) Writing Period: 3 hour duration Study Period: 15 minutes duration Permitted Materials: One A4 page with notes on both
More informationCSE Lecture In Class Example Handout
CSE 30321 Lecture 07-08 In Class Example Handout Part A: J-Type Example: If you look in your book at the syntax for j (an unconditional jump instruction), you see something like: e.g. j addr would seemingly
More informationInstruction Set Architecture
Computer Architecture Instruction Set Architecture Lynn Choi Korea University Machine Language Programming language High-level programming languages Procedural languages: C, PASCAL, FORTRAN Object-oriented
More informationSubroutines and the Stack
3 31 Objectives: A subroutine is a reusable program module A main program can call or jump to the subroutine one or more times The stack is used in several ways when subroutines are called In this lab
More informationFunctions in MIPS. Functions in MIPS 1
Functions in MIPS We ll talk about the 3 steps in handling function calls: 1. The program s flow of control must be changed. 2. Arguments and return values are passed back and forth. 3. Local variables
More informationCSE351 Spring 2018, Midterm Exam April 27, 2018
CSE351 Spring 2018, Midterm Exam April 27, 2018 Please do not turn the page until 11:30. Last Name: First Name: Student ID Number: Name of person to your left: Name of person to your right: Signature indicating:
More informationFull Name: CISC 360, Fall 2008 Example of Exam
Full Name: CISC 360, Fall 2008 Example of Exam Page 1 of 0 Problem 1. (12 points): Consider the following 8-bit floating point representation based on the IEEE floating point format: There is a sign bit
More informationCSE 351 Midterm - Winter 2015
CSE 351 Midterm - Winter 2015 February 09, 2015 Please read through the entire examination first! We designed this exam so that it can be completed in 50 minutes and, hopefully, this estimate will prove
More informationBranch Addressing. Jump Addressing. Target Addressing Example. The University of Adelaide, School of Computer Science 28 September 2015
Branch Addressing Branch instructions specify Opcode, two registers, target address Most branch targets are near branch Forward or backward op rs rt constant or address 6 bits 5 bits 5 bits 16 bits PC-relative
More informationCMPSCI 201 Fall 2005 Midterm #2 Solution
CMPSCI 201 Fall 2005 Midterm #2 Solution Professor William T. Verts 10 Points Convert the decimal number -47.375 into (a) binary scientific notation (i.e., ±1.xxxx 2 Y ), and (b) the equivalent binary
More informationArchitecture. Digital Computer Design
Architecture Digital Computer Design Architecture The architecture is the programmer s view of a computer. It is defined by the instruction set (language) and operand locations (registers and memory).
More information6.004 Tutorial Problems L3 Procedures and Stacks
6.004 Tutorial Problems L3 Procedures and Stacks RISC-V Calling Conventions: Caller places arguments in registers a0-a7 Caller transfers control to callee using jal (jump-and-link) to capture the urn address
More information16.317: Microprocessor Systems Design I Spring 2015
16.317: Microprocessor Systems Design I Spring 2015 Exam 2 Solution 1. (16 points, 4 points per part) Multiple choice For each of the multiple choice questions below, clearly indicate your response by
More information1 /18 2 /16 3 /18 4 /26 5 /22
M A S S A C H U S E T T S I N S T I T U T E O F T E C H N O L O G Y DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE 6.004 Computation Structures Fall 2018 Quiz #2 1 /18 2 /16 3 /18 4 /26 5 /22
More informationProblem maximum score 1 35pts 2 22pts 3 23pts 4 15pts Total 95pts
University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences CS61c Summer 2001 Woojin Yu Midterm Exam This is a closed-book exam. No calculators
More informationMIPS Datapath. MIPS Registers (and the conventions associated with them) MIPS Instruction Types
1 Lecture 08 Introduction to the MIPS ISA + Procedure Calls in MIPS Longer instructions = more bits to address registers MIPS Datapath 6 bit opcodes... 2 MIPS Instructions are 32 bits More ways to address
More informationExam 1. Date: February 23, 2018
Exam 1 Date: February 23, 2018 UT EID: Printed Name: Last, First Your signature is your promise that you have not cheated and will not cheat on this exam, nor will you help others to cheat on this exam:
More informationCSE 351 Midterm - Winter 2015 Solutions
CSE 351 Midterm - Winter 2015 Solutions February 09, 2015 Please read through the entire examination first! We designed this exam so that it can be completed in 50 minutes and, hopefully, this estimate
More informationICS DEPARTMENT ICS 233 COMPUTER ARCHITECTURE & ASSEMBLY LANGUAGE. Midterm Exam. First Semester (141) Time: 1:00-3:30 PM. Student Name : _KEY
Page 1 of 14 Nov. 22, 2014 ICS DEPARTMENT ICS 233 COMPUTER ARCHITECTURE & ASSEMBLY LANGUAGE Midterm Exam First Semester (141) Time: 1:00-3:30 PM Student Name : _KEY Student ID. : Question Max Points Score
More informationLab 4 : MIPS Function Calls
Lab 4 : MIPS Function Calls Name: Sign the following statement: On my honor, as an Aggie, I have neither given nor received unauthorized aid on this academic work 1 Objective The objective of this lab
More informationStored Program Concept. Instructions: Characteristics of Instruction Set. Architecture Specification. Example of multiple operands
Stored Program Concept Instructions: Instructions are bits Programs are stored in memory to be read or written just like data Processor Memory memory for data, programs, compilers, editors, etc. Fetch
More informationSystem Software Assignment 1 Runtime Support for Procedures
System Software Assignment 1 Runtime Support for Procedures Exercise 1: Nested procedures Some programming languages like Oberon and Pascal support nested procedures. 1. Find a run-time structure for such
More information/ 28 HLL assembly Q4: Conditional instructions / 40 TOTAL SCORE / 100 EXTRA CREDIT / 10
16.317: Microprocessor Systems Design I Fall 2014 Exam 2 November 5, 2014 Name: ID #: For this exam, you may use a calculator and one 8.5 x 11 double-sided page of notes. All other electronic devices (e.g.,
More informationControl Instructions. Computer Organization Architectures for Embedded Computing. Thursday, 26 September Summary
Control Instructions Computer Organization Architectures for Embedded Computing Thursday, 26 September 2013 Many slides adapted from: Computer Organization and Design, Patterson & Hennessy 4th Edition,
More informationControl Instructions
Control Instructions Tuesday 22 September 15 Many slides adapted from: and Design, Patterson & Hennessy 5th Edition, 2014, MK and from Prof. Mary Jane Irwin, PSU Summary Previous Class Instruction Set
More informationExam 1. Date: February 23, 2016
Exam 1 Date: February 23, 2016 UT EID: Printed Name: Last, First Your signature is your promise that you have not cheated and will not cheat on this exam, nor will you help others to cheat on this exam:
More informationFormat. 10 multiple choice 8 points each. 1 short answer 20 points. Same basic principals as the midterm
Final Review Format 10 multiple choice 8 points each Make sure to show your work Can write a description to the side as to why you think your answer is correct for possible partial credit 1 short answer
More information16.317: Microprocessor Systems Design I Fall 2015
16.317: Microprocessor Systems Design I Fall 2015 Exam 2 Solution 1. (16 points, 4 points per part) Multiple choice For each of the multiple choice questions below, clearly indicate your response by circling
More informationCprE 288 Introduction to Embedded Systems ARM Assembly Programming: Translating C Control Statements and Function Calls
CprE 288 Introduction to Embedded Systems ARM Assembly Programming: Translating C Control Statements and Function Calls Instructors: Dr. Phillip Jones 1 Announcements Final Projects Projects: Mandatory
More informationLectures 5. Announcements: Today: Oops in Strings/pointers (example from last time) Functions in MIPS
Lectures 5 Announcements: Today: Oops in Strings/pointers (example from last time) Functions in MIPS 1 OOPS - What does this C code do? int foo(char *s) { int L = 0; while (*s++) { ++L; } return L; } 2
More informationECE331: Hardware Organization and Design
ECE331: Hardware Organization and Design Lecture 15: Midterm 1 Review Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Basics Midterm to cover Book Sections (inclusive) 1.1 1.5
More informationTrap Vector Table. Interrupt Vector Table. Operating System and Supervisor Stack. Available for User Programs. Device Register Addresses
Chapter 1 The LC-3b ISA 1.1 Overview The Instruction Set Architecture (ISA) of the LC-3b is defined as follows: Memory address space 16 bits, corresponding to 2 16 locations, each containing one byte (8
More information