Advanced Synthesis Techniques

Transcription

1 Advanced Synthesis Techniques

2 Reminder From Last Year Use UltraFast Design Methodology for Vivado Recommendations for Rapid Closure HDL: use HDL Language Templates & DRC Constraints: Timing Constraint Wizard, DRC Iterate in Synthesis (converge within 300ps) Real problems seen post synthesis (long path ) Faster iterations & higher impact Improve area, timing, power Only then, iterate in next steps opt, place, phys_opt, route, phys_opt Tools >Report >Report DRC Worst path post Synthesis: 4.3ns 3 levels of logic! Worst path post Route: 4.ns 4 levels of logic

3 Advanced Synthesis Techniques Overview Advantages of C Synthesis over RTL Synthesis Advance Synthesis Techniques for Design Closure Case Study: design closure at Synthesis level

4 HLS & IP Integrator (IPI) vs. RTL Synthesis VHDL, Verilog: RTL 00k RTL (VHDL) lines (VHDL) VHDL-2008, SV: 50k lines Test Bench Test Test Bench (System (System Bench C) C) (driver level) RTL C++ RTL (VHDL) code (VHDL) (5k lines)) Test Bench Test Test Bench (System (System Bench C) C) (application) Minimal test RTL Sim. Verification advantage: e.g. video processing RTL: frame per ~5 hours C++: frame per second C Debug Exhaustive functional tests RTL Synthesis Design closure HLS IPI Design closure RTL Synth P&R P&R HW System Debug Exhaustive functional tests HW System Debug System-level Debug Actual example: Traditional Flow 240 people*mo o 0 people o 2 years 5x faster HLS Based Flow 6 people*mo o 2 people o 8 month Faster for derivative designs C++ reuse Scales with parameters Device independent

5 HLS Automates Micro-architecture Exploration while (i++) for j =0.. N y(i) = y(i) + b(j) * x(i-j) Project specification Architecture choices while (i++) for j =0.. N y(i) = y(i-j) +b(j) * x(i) x(n) Z - Z - Z - x(n) b 0 b b 2 b m- b 0 b b 2 b m- X X X X X X X X Micro-architecture choices Z - + Z - + Z - + Algorithmic delay x(n) b x(n) 0 X + X + Fully parallel: N DSP + cascade X + Pipeline register x(n) + Fully Folded: DSP (default) X X X Fully parallel: N DSP no cascade

6 HLS Micro-Architecture Exploration while () M3(i) = M(i-2) * C2 A(i) = M3(i) + x(i) M2(i) = M(i-) * C A2(i) = A(i) + M2(i) M(i) = A2(i) * C0 i++ C++ A A2 M M2 x[i] M3 c 0 c c 2 Z - Z - Dataflow Graph RTL Schedule : 4 cycles Sequential process (CPU model) Minimal HW Resources: MULT, ADD M3 A M2 A2 M i 4 i+ 28 M3 Z - A M2 A2 Z -2 M M3 Schedule 2: 0 cycles Parallelism within each iteration Better performance (~29%) 2 MULT, ADD M3 A A2 M M2 i 0 i+ Z -2 M3 A A2 M Z - M2 20 M3 i+2 Schedule 3: 9 cycles Loop pipelining Best performance (~36%) 2 MULT, ADD M3 A A2 M M2 i 9 i+ Z -2 M3 A A2 M Z - M2 8 M3 i+2

7 LUT6 Cross-probing Vivado Synthesis Flow Syntax check Build file hierarchy Design hierarchy Unroll loops Build Logic: Arithmetic RAM FSM Boolean logic XDC VHDL, Verilog VHDL-2008, SystemVerilog more compact: advanced types verification friendly: UVM, SVA Analyze Elaborate Module generators RTL Optimizations Boolean optimization Technology mapping Optimize & Map P&R or DCP

8 Architecture-Aware Coding Priority Encoders Loops Clocks & Resets Directives & Strategies Case Study

9 Architecture Aware DSP HDL code needs to match DSP hardware (e.g. DSP48E2) Signage, width of nets, optimal pipelining Signed 27 bit A 27 ACC B 27 C XOR EQ Verify that DSP are inferred efficiently Signed arithmetic with pipelining Use templates & Coding style examples: Complex multiplier Squarer (UG90) Multiply-accumulate Dynamic pre-adder FIR (UG579) Large accumulator Rounding (205.3) XOR (206.)

10 DSP Block Inference Improvements (a b) 2 (a + b) 2 Squarer: DSP Complex multiplier: 3 DSP (a+bi)*(c+di) = ((c-d)*a + S) + ((c+d)*b + S)i with S=(a-b)*d A B X X+ +X+ Re Im Wider arithmetic requires more pipelining e.g. MULT 44x35 requires 4 MULT 27x8 & ADD A B Synthesis A B Pipelined MULT 44x35 in HDL Mapped to 4 DSP Blocks (27x8 MULT) Verify proper inference for full DSP block performance!

11 Architecture-Aware RAM & ROM HDL code needs to match BRAM Architecture Registered address (sync read), optional output register 32K configurations Width= x Depth=2 5 (32K) = 32Kx Width=2 x Depth=2 4 (6K) = 6Kx2 Width=32 x Depth=2 0 (K) = Kx32 36K configuration Width=36 x Depth=2 0 (K) = Kx36 Wider & Deeper Memories Automatically inferred by Synthesis RAMB36 addr addr 32xK out Q Verify that BRAM are inferred efficiently! Example: single port RAM

12 RAM Decomposition: Example 32Kx32 RAM 32Kx Kx32 32 Kx x 32Kx x Kx x 4x... Kx32 LUTs 32 32Kx Kx MUX W= D=5 W=32 D=0 W=32 D=0 High Performance & Power (default w/ timing constraints) level, 32 BRAM active Low Power & Performance UltraScale cascade-mux 32 levels, BRAM active Performance/Power Trade-off Hybrid LUT & UltraScale Cascade 4 levels, 4 BRAM active (* cascade_height = 32 *) (* cascade_height = 4 *) Verify that BRAM are decomposed efficiently!

13 RAM & ROM Recommendations BRAM Reg BRAM Reg BRAM Reg Reg BRAM Reg Use pipeline Reg for performance No logic in-between No Fanout In same hierarchy! BRAM slack<0 BRAM slack>0 Reg Reg Reg Reg Reg Run phys_opt to move Reg in & out based on timing Add extra pipeline for best performance! Verify that BRAM are pipelined efficiently!

14 Beware of Priority Logic if (c0) q = a0; else if (c) q = a; else if (c2) q = a2; else if (c3) q = a3; else if (c4) q = a4; else if (c5) q = a5; if (c0) q = a0; if (c) q = a; if (c2) q = a2; if (c3) q = a3; if (c4) q = a4; if (c5) q = a5; a5 Priority encoded logic long paths a4 c5 a3 c4 a2 c3 a c2 a0 c c0 Priority logic will hurt Timing Closure! a0 a c0 Removing else s won t help!! a2 c a3 c2 a4 c3 a5 c4 c5

15 Priority Logic with for loops flag = 0; for (i=0 ; i<3 ; i=i+) if (c[i]) flag = ; Same as if if if flag = 0; for (i=0 ; i<3 ; i=i+) if (c[i]) begin flag = ; break; //SystemVerilog end Same as if else if else if break won t help!! 0 c[26] c[27] c[30] c[29] c[28] c[3] 0 c[5] c[4] c[3] c[2] c[] c[0] break does not reduce logic! Best code in this case: flag = c Think Simple!

16 Priority Logic with case Statement case (c) v0: q=a0; v: q=a; v2: q=a3; v3: q=a4; v4: q=a5; In Verilog: CASE (c) //synthesis parallel_case (watch for simulation mismatch!) In SystemVerilog: unique case (c) // works with if too a5 CASE won t help either! (note: values are variables) a4 c==v5 a3 c==v4 a2 c==v3 a BAD c==v2 a0 c==v c==v0 a0 c v0 a c v a2 c v2 a3 c v3 a4 c v4 GOOD If conditions are mutually exclusive, make it clear! Note: please use complete conditions.v full_case (simulation may not match) or default & assign don t_care.sv priority (for case & if)

17 Priority Logic Which Should Not Be! if (c0) q = a0; else if (c) q = a; else if (c2) q = a2; else if (c3) q = a3; else if (c4) q = a4; else if (c5) q = a5; a a2 a3 a4 a5 c0 = (S == 0); c = (S == ); c2 = (S == 2); c3 = (S == 3); c4 = (S == 4); -hot conditions (here: binary encoded) a0 S 2 S S 0 Automated in most cases Even with registered conditions! a0 S 0.2 a S 0.2 a2 S 0.2 a3 S 0.2 a4 S 0.2 a5 S 0.2 unique if (c0) in SystemVerilog a0..7 case (S) 0: q = a0 : q = a 2: q = a2 or: q = A[S] S a0..3 S 0 S BAD GOOD GOOD If conditions are mutually exclusive, do not use a priority logic Use unique if in SystemVerilog a4..7 S 0 S S 2

18 Parallelizing Priority Logic When you can t avoid O(n), you still can! a63 0 a5 0 c5 a4 if c0 c63 64 deep 0 c4 a3 0 c3 a2 0 c2 a 0 c a0 0 c0 if c32 c63 32 deep if c0 c3 32 deep 0 c0 c3 2 deep (log 6 (32)) c63 BAD: N deep GOOD: N/2 + deep... or N/4 + 2 or log(n) recursively Improve timing even when conditions are not mutually exclusive!

19 Beware of Loop Unrolling Avoid if c = 0; for (i=0 ; i<8 ; i=i+) if (a[i]) c = c+; Get rid of if c = 0; for (i=0 ; i<8 ; i=i+) c = c+a[i]; c = a[0] + a[] + a[2] + a[3] + a[4] + a[5] + a[6] + a[7]; a[0] a[7] 0 + a[7] + a[6] + a[0] c a[] a[2] a[3] a[4] a[6] a[5] + c BAD: area & depth O(N) GOOD: area & depth log 3 (N) if in loops can seriously hurt timing!

20 Beware of Loop Unrolling Arithmetic s Q = 0 for i = 0 to 3 for j = 0 to 3 Q = Q+A+i+j Q = = 6*A + 48 = A<< Q = (A + 3) << 4 Q = 0+ A A+0+ + A A+0+3 A++0 + A++ + A++2 + A++3 A A+2+ + A A+2+3 A A+3+ + A A+3+3 A[N-:4] 48 + Q[N-4:0] A[N-5:0] 3 + Q[N-:4] BAD: up to 36 N bit adder GOOD: N-3 bit adder BETTER: N-4 bit adder Loops (in general) can hurt timing! Here: symbolic arithmetic optimization may not happen

21 Avoid Gated Clock Transformation Very common in ASIC design (low power) Consolidate the clocks to minimize clock skew D Q low-skew network (BUFG) D Q c CE (latched on ~c) clk ASIC FPGA c CE CE clk edged detector D Q D Q D Q D Q c clk clk c clk CE clk BAD: 2 clocks, gated GOOD: clock Avoid gated clocks they will hurt timing closure (will cause clock skew)

22 Avoid [Async] Resets What we recommended Reduce the number of control sets {clk, rst, ce} Avoid Reset / avoid Async Reset D Q D Q D Q does this really remove reset? CE clk CE clk CLR clk rst BAD: Attempt to remove Reset created Enable and Reset is still Async Verify that removing Reset did not add Enables

23 DIRECT_ENABLE/DIRECT_RESET Guides Synthesis to directly connect net to DFF control pin When Synthesis is choosing to not use the reset or enable When there are multiple possibilities of enable or set/reset D Q D D Q direct_enable CE CE clk CE clk RST D D clk Q direct_reset RST D Q R clk Guide Synthesis to connect a signal to Enable, Reset

24 RTL Synthesis: New Strategies Vivado RTL Synthesis has now 8 Strategies Each Strategy is a combination of options & directives Directives have a specific purpose For quick pipe-cleaning iterations FLow_RuntimeOptimized For best area Flow_AreaMultThresholdDSP Flow_AreaOptimized_medium Flow_AreaOptimized_high For performance Vivado_Synthesis_Default Flow_PerfOptimized_high Flow_PerfThresholdCarry Strategies in Vivado (synthesis options) For congested designs Flow_AlternateRoutability Taking the best of all Strategies can give you 0% better QoR

25 Case Study Problem Area explosion & bad timing in a design Locating the cause of the issue Find offending module & synthesize it Out Of Context Look for suspicious operators on Elaborated view (how??) Cross-probe to source files Resolution Fix the source code and/or use synthesis options

26 Case Study: Locating the Cause of the Issue Look for suspicious operators Ctrl-F in Elaborated Schematic Select suspicious operators (here: MULT, MOD ) Press F4 to view schematic Press F7 to cross-probe

27 Case Study: More Useful / Fun Tips Double Click to expand paths Go back & forth Cross-probe from HDL to schematic!!! (RTL or gate) Select text & right-click Press F4

28 Case Study: Analysis of QoR Issue Should this code generate arithmetic s? array(263..0) of std_logic_vector(3..0) array(23..0) of std_logic_vector(3..0) 47,000 LUT 7,000 CARRY4 k DFF cnt (values: 0..0) * 24 + i (values: 0..23) 264 constants No MULT, ADD, or MOD necessary! How to fix it? Please propose a code change to improve QoR...

29 Case Study: Resolution Original Code Solution 47,000 LUT 7,000 CARRY4 k DFF LUT 0 CARRY4 k DFF # timing closure technique: careful analysis of Synthesis results!

30 Conclusion Use HLS & IPI when you can 5X more productive for design & verification HLS often achieves better quality of results Iterate in Synthesis for design closure! Adopt SystemVerilog or VHDL-2008 for higher productivity Use templates for big blocks Investigate QoR issues Locate possible Synthesis QoR issues Recode or use tools options as needed Final gunshot approach try different Strategies Do not move to P&R until timing is closed (within 300 ps)