Chapter 5 Global Timing Constraints. Global Timing Constraints 5-1

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1 Chapter 5 Global Timing Constraints Global Timing Constraints 5-1

2 Objectives After completing this module, you will be able to Apply timing constraints to a simple synchronous design Specify global timing constraints and pin assignments with the Constraints Editor Global Timing Constraints 5-2

3 Outline Introduction The Period Constraint The Offset Constraint The Constraints Editor Summary Global Timing Constraints 5-3

4 What Effects o Timing Constraints Have on Your Project? The Implementation tools don t try to find the place and route that will obtain the best speed Instead, the Implementation tools try to meet your performance expectations Performance expectations are communicated with timing constraints Timing Constraints improve the design performance by placing logic closer together so shorter routing resources can be used Note that when we discuss using the Constraint Editor, we are referring to the esign Manager Constraints Editor Global Timing Constraints 5-4

5 What Needs Constraining? Internal clock speed for one or more clocks I/O speed Logic using multi-cycle clocks Pin to Pin timing Pin Locations & Logic Locations I/O Speed Clk & CE Speed I/O Speed X CLK Y Z<0:9> Logic Locations 1 Level of Logic 2 Levels of Logic OUT1 OUT2 Pin Locations Pin Locations Pin 2 Pin Speed Global Timing Constraints 5-5

Without Timing Constraints This design had no timing constraints or pin assignments entered with the design when it was implemented Note the logical structure of the placement and pins.

6 Without Timing Constraints This design had no timing constraints or pin assignments entered with the design when it was implemented Note the logical structure of the placement and pins. Xilinx recommends that you compile your design at least once without timing constraints or pin assignments This design has a maximum system clock frequency of 50 MHz Global Timing Constraints 5-6

With Timing Constraints This is the same design with three global timing constraints entered with the Constraints Editor It has a maximum system clock

7 With Timing Constraints This is the same design with three global timing constraints entered with the Constraints Editor It has a maximum system clock frequency of 60 MHz Note how most of the logic is placed closer to the edge of the device where the pins have been placed Global Timing Constraints 5-7

8 More About Timing Constraints Timing constraints should be used to define your performance objectives Specifying tight timing constraints will increase your compile time Specifying unrealistic constraints will cause the Flow Engine to stop Use the Logic Level Timing Report to determine if your constraints are realistic (refer to the Reading Reports module) After implementing your design, review the Post Layout Timing Report to determine if your design performance objectives were met If your constraints were not met, use the Timing Analyzer to determine the cause Global Timing Constraints 5-8

9 Path End Points Timing constraints optimize delay paths between path endpoints. Path endpoints can be pads, flip-flops, latches, and RAMs Making timing constraints becomes easier when you realize that timing constraints create groups of path endpoints and communicate a timing specification between these groups Since delay paths may require signals to go through multiple function generators in series, optimizing between path endpoints requires the Implementation tools to place logic closer together Global Timing Constraints 5-9

10 Review If the arrows are constrained paths, what are the Path End Points in this circuit? The Path End Points are flip-flops o all of the registers have anything in common? The registers are all clocked by the same signal. A constraint that references this net could constrain all delay paths between all of the registers in the design AATA FLOP1 FLOP2 FLOP3 OUT1 CLK BUFG FLOP4 FLOP5 BUS [7..0] OUT2 CATA = Combinatorial Logic Global Timing Constraints 5-10

11 Outline Introduction Period Constraint The Offset Constraint The Constraint Editor Summary Global Timing Constraints 5-11

12 Period Constraint In this example the Period constraint optimizes all delay paths between flip-flops The Period constraint does NOT optimize delay paths from input pads to output pads (purely combinatorial), paths from input pads to flip-flops, or paths from flip-flops to output pads AATA FLOP1 FLOP2 FLOP3 OUT1 CLK BUFG FLOP4 FLOP5 BUS [7..0] OUT2 CATA = Combinatorial Logic Global Timing Constraints 5-12

13 The Period Constraint A synchronous element is a flip-flop, latch, or a synchronous RAM The Period constraint covers paths Between synchronous elements which are clocked by the reference net Synchronous elements are grouped by the clock signal driving them. This is called forward propagation and enables constraining large pieces of logic with a single constraint Global Timing Constraints 5-13

14 Some Features of the Period Constraint The PERIO constraint automatically accounts for the extra delay caused by inverters and global clock buffers placed on clock signals This provides the most accurate timing information The PERIO constraint automatically accounts for unequal clock duty cycles FF1 FF2 Assume: 50% duty signal on CLK BUFG Period of 20ns Since FF2 will be clocked on the falling edge of CLK, the delay between the two flip-flops will actually be constrained to 20ns - 10ns = 10ns CLK INV Global Timing Constraints 5-14

15 The Pad-to-Pad Constraint Purely combinatorial delay paths do not contain any synchronous elements Purely combinatorial delay paths start and end at I/O pads and are often left unconstrained by users Placing a Pad-to-Pad constraint is essential for completely constraining a design Global Timing Constraints 5-15

16 Review Which paths are constrained by a PERIO constraint on CLK1? FLOP to LATCH Which paths are constrained by a Pad-to-Pad constraint? PAC to OUT2 PAA FLOP LATCH OUT1 CLK1 G CLK2 PAB BUFG RAM OUT2 BUFG PAC Global Timing Constraints 5-16

17 Outline Introduction The Period Constraint The Offset Constraint The Constraints Editor Summary Global Timing Constraints 5-17

18 Offset Constraint In this example, the Offset constraint optimizes delay paths from input pads to flip-flops and paths from flip-flops to output pads Offset In Offset Out AATA FLOP FLOP FLOP OUT1 CLK BUFG FLOP FLOP BUS [7..0] OUT2 CATA = Combinatorial Logic Global Timing Constraints 5-18

19 The Offset Constraint The Offset constraint covers paths From input pads to synchronous elements clocked by the reference net (Offset In) ---> Input elay From synchronous elements to output pads clocked by the reference net (Offset Out) --> Output elay Note, that this constraint does not cover paths Between synchronous elements From pads to pads (purely combinatorial paths) Global Timing Constraints 5-19

20 Some Features of the Offset Constraint The OFFSET constraint automatically accounts for the extra delay caused by inverters and global clock buffers placed on clock signals This provides the most accurate timing information This increases the amount of time for input signals to arrive at synchronous elements This reduces the amount of time for output signals to arrive at output pins Global Timing Constraints 5-20

21 Review Which paths are constrained by an Offset In and Offset Out constraint in this circuit? Offset In: PAA to FLOP and PAB to RAM Offset Out: LATCH to OUT1, LATCH to OUT2, and RAM to OUT1 CLK PAA FLOP LATCH G OUT1 PAB BUFG RAM OUT2 PAC Global Timing Constraints 5-21

22 Basic Global Timing Constraints ( using the FROM-TO Syntax) UCF TIMESPEC command using default keywords: TIMESPEC TS_C2S=FROM:FFS:TO:FFS:30; TIMESPEC TS_P2S=FROM:PAS:TO:FFS:25; TIMESPEC TS_P2P=FROM:PAS:TO:PAS:26; TIMESPEC TS_C2P=FROM:FFS:TO:PAS:9; TS_P2S TS_C2S TS_C2P OUT1 CLK OUT2 TS_P2P Global Timing Constraints 5-22

23 Global Constraint Review (1) Example: CLK1 has a period of 25 ns (50% duty cycle), and CLK2 has a period of 12 ns (50% duty cycle). Fill in the Global form for this circuit (see next page). Assume zero delay for setup, pads, CLK-, etc. SAINT<31:0> WAG 22 ns FF1 25 ns FF2 15 ns OG_SLOW CLK1 GRAYHOUN 10 ns FF3 12 ns FF4 10 ns OG_GONE CLK2 TOP_OG Global Timing Constraints 5-23

24 Use the Advanced form for Speed Offsets Global Timing Constraints 5-24 Step 1: efine specific path endpoints (optional) Step 2: Assign timing constraints Offsets can replace some Global and Port commands when external specs are known Speed Exceptions such as False Paths and Multi-cycle paths

25 Fast/Slow Speed Exceptions Speed exceptions are controlled with the Advanced -> From: To options From specifies the source of the constraint To specifies the endpoint of the constraint You can create your own groups of endpoints using the Time Group constraints, or use the default groups: Pads, Flip_Flops, RAMs, Latches Global Timing Constraints 5-25

26 Outline Introduction The Period Constraint The Offset Constraint The Constraints Editor Summary Global Timing Constraints 5-26

27 Making Pin Assignments With the Ports Tab Pad locations and Slew Rate can be assigned on a pin-by-pin basis Place pin assignments late in the design cycle Early pin locking can make obtaining performance objectives more difficult To make Pin Assignments, double-click on the appropriate box under the Location heading Then type P60 to assign the signal to Pin 60 of the device Global Timing Constraints 5-27

28 Making Pin Assignments with the Ports Tab Prohibit I/O Locations when saving pins for a team design project Prohibiting is also useful for handling dualpurpose pins, such as configuration pins Global Timing Constraints 5-28

29 Making Period and Pad-to-Pad Constraints With the Global Tab Clock Periods can be made by clicking on the Global tab and specifying a period length for each clock signal ouble-click here to make a period constraint A global Pad-to-Pad constraint can be entered here Global Timing Constraints 5-29

30 Period Constraint Options After double-clicking under the Period heading, the Clock Period dialog box opens This allows customizing the constraint to the duty-cycle and rising or falling clock edge It is also possible to place timing constraints relative to other timing constraints. This is useful for designs with multiple clock signals and multi-cycle paths Global Timing Constraints 5-30

31 Making Offset Constraints with the Constraints Editor Pad to Setup = Offset In Clock to Pad = Offset Out Global Offset IN/OUT constraints can be made by clicking on the Global tab Global Timing Constraints 5-31

32 Outline Introduction The Period Constraint The Offset Constraint The Constraint Editor Summary Global Timing Constraints 5-32

33 Review uestion If the internal delay on an input signal A0_IN is 14 ns, the internal delay on the output A0_OUT is 12 ns, and the design should perform with a period of 40 ns, what constraints should be placed in the the Constraints Editor? etermined by Software Tinput=14ns 40ns etermined by Software Toutput=12ns A0_IN CLK FF1 FF2 A0_OUT Global Timing Constraints 5-33

34 Answer How would you make these constraints in the Constraints Editor? Global Timing Constraints 5-34

35 Summary Performance expectations are communicated with timing constraints The PERIO constraint improves delay paths between synchronous elements The OFFSET constraint improves delay paths from input pins to synchronous elements, and paths from synchronous elements to output pins The Constraints Editor allows you to create timing constraints Global Timing Constraints 5-35

IDEA! Avnet SpeedWay Design Workshop

IDEA! Avnet SpeedWay Design Workshop The essence of FPGA technology IDEA! 2 ISE Tool Flow Overview Design Entry Synthesis Constraints Synthesis Simulation Implementation Constraints Floor-Planning Translate Map Place & Route Timing Analysis