GUIDE TO USE OF PIC 16F690 EEProm. The 16F690 PIC has a 256 byte EEProm (mapped to 0x x21FF).

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1 GUIDE TO USE OF PIC 16F690 EEProm The 16F690 PIC has a 256 byte EEProm (mapped to 0x x21FF). PRESET DATA (WITH PROGRAM CODE) Data can be preset by use of the de operator: Org 0x21XX de de etc. 0x01,0x02 0xFA Bytes are allocated memory sequentially, starting at the given org address. PROGRAMMED READING AND WRITING Two control registers, EECON1 and EECON2 (both in bank 3) are used to control reading / writing. 8-bit data is sourced, for writing from register EEDAT and is sent to, when reading, register EEDAT. The address in EEProm for reading or writing must be specified in EEADR. (EEDAT and EEADR both reside in bank 2). EEADR is the offset 0x00..0xFF from the base address of the EEProm. (NB: ensure correct bank selection for the above special registers) (NB: the program memory can be read/written in a similar way. Because of the addressing range and the 13-bit wide program memory additional registers must be used for the high data byte and the high address byte, EEDATH and EEADRH)

2 Code to do a basic 1-byte read: SingleByteREad: ; EEADR is preloaded with address (00..FF) in EEProm ; w has byte read on. bsf STATUS,RP0 bcf EECON1,EEPGD ; EEPGD=0 for EEPROM bsf EECON1,RD ; RD=1 (read EEProm) ; select bank 2 movf EEDAT,w ; Get byte read from EEProm Explanation of the code above (Preload EEADR with EEProm address to be read prior to calling function) Select EEProm (not program memory) (EECON1,EEPGD) Request a READ. Set RD bit in EECON1 (self-clears after read) (data is read and placed into EEDAT in one m/c code cycle) Move read data from EEDAT to register w ready for moving elsewhere on

3 Code to do a 1-byte write: EE_AwaitByteWrite: ; EEADR has eeprom write address, EEDAT has data byte to be written ; only use for a single byte. Bank 0 selected on bsf STATUS,RP0 bcf EECON1,EEPGD ; select EEProm bsf EECON1,WREN ; unlock eeprom. Allow writing movlw 0x55 movwf EECON2 ; write 0x55 movlw 0xAA movwf EECON2 ; write 0xAA bsf EECON1,WR ; initiates erase & write cycle WaitUntilDone: btfsc EECON1,WR ; end of write cycle? (cleared by h/w) goto WaitUntilDone ; about 4ms to wait bcf EECON1,WREN ; lock eeprom. Disallows writes bcf PIR2,EEIF ; clear EEIF flag ; byte written NB: The above code is NOT RECOMMENDED because it waits for the write operation to complete (about 4ms) in which time many thousands of instructions could have been processed! This is a simple write for explanation only. (Preload EEADR with EEProm address to be written prior to calling function) (Preload EEDAT with data to be written to this address prior to calling function) Select EEProm (not program memory) (EECON1,EEPGD) Unlock Eeprom (enable write) set EECON1,WREN Now perform the magic sequence : Write to EECON2, 0x55 Write to EECON2, 0xAA Request a WRITE. Set WR bit in EECON1 (self-clears after write) (NB: If interrupts are being used, disable interrupts during the above sequence) (the write sequence has started but will take a long time to complete, about 4ms) Lock Eeprom (disable write) clear EECON1,WREN Wait for the WR bit to clear. This indicates completion. The above code loops within the function and only s on completion. A better way of doing this is to and to detect completion by use of the EEIF flag (interrupt flag in PIR2). This can either be polled in the main loop or can cause an interrupt.

4 MULTIPLE BYTE READS AND WRITES These are more practical functions than the basic, single byte operations. Indirect addressing is used for the read destination address and for the write source address. Reading ; EEPROM READ ; Preload: Pointer_A, Pointer_B, EE_ByteCount and DEST_IRP_BIT in GenFlags ; A contiguous block of data is copied from Pointer_A (EEPROM LS ADDRESS) to Pointer_B (RAM LS ADDRESS) ; Pointer_A is the source pointer(address in EEProm 0x00..0xFF). Pointer_B is the destination pointer (LS byte of file reg) in RAM. ; DEST_IRP_BIT for the destination pointer address must be preloaded (0=banks 0/1, 1=bank 2) ; EE_ByteCount must be loaded with the number of contiguous bytes to be copied. ; Call with any bank selected. The same bank will be selected on ReadEEProm: movf STATUS,w movwf Saved_Status ; save status (inc. current bank) bsf STATUS,RP0 movf Pointer_A,w ; get source bsf STATUS,RP1 ; select bank 2 movwf EEADR ; load source address (reading EEPROM) bcf STATUS,IRP ; asume IRP=0 btfsc GenFlags,EE_DEST_IRP_BIT ; if IRP_BIT_B set then bsf STATUS,IRP ; make IRP=1 movf Pointer_B,w ; get destination movwf FSR ; load destination address (RAM-based) CopyEEProm: movf EE_ByteCount,f btfsc STATUS,Z goto ExitReadEEProm ; (bank 0 selected) ; all bytes copied? ; if not, skip ; end bsf STATUS,RP0 bcf EECON1,EEPGD ; EEPGD=0 for EEPROM bsf EECON1,RD ; RD=1 (read EEProm) ; select bank 2 movf EEDAT,w ; Get byte read from EEProm movwf INDF ; and store it in ram incf EEADR,f ; next EEProm Address

5 incf FSR,f ; next RAM Address decf EE_ByteCount,f ; one less byte to copy goto CopyEEProm ; loop ExitReadEEProm: movf Saved_Status,w movwf STATUS ; restore status (inc. bank number) ; EEPROM READ This code uses the multi-bank addressable registers (in the range 0xX70..0xX7F). It also stores and restores the content of the status register (so it can be called with any bank selected. Despite bank changing, the original bank will be selected on ). Preload: Pointer_A to the source of the data (offset in EEProm 0x00..0xFF) Pointer_B to the required destination of the data in banked ram (register file). If reading into bank 0 or 1 clear DEST_IRP_BIT. If reading into bank 2 set DEST_IRP_BIT. EE_ByteCount with the number of sequential bytes to be read. Status register saved. Pointer_A is copied to EEADR Pointer_B is copied to FSR Loop begins: Status IRP bit is copied from EE_DEST_IRP_BIT Read sequence occurs (as in single byte read) Read data is copied to INDF EEADR is incremented (next data byte source) FSR is incremented (next data byte destination) EE_ByteCount is decremented. If zero, exit loop. Loop end Status register restored.

6 Writing: ; EEPROM WRITE ; Preload: Pointer_A, Pointer_B, EE_Wr_ByteCount, GenFlags,EE_SOURCEIRP_BIT ; A contiguous block of data is copied from Pointer_A (LS RAM ADDRESS) to Pointer_B (LS EEPROM ADDRESS) ; Pointer_A is the source pointer(ls byte of RAM). Pointer 2 is the destination pointer (address in EEProm 0x00..0xFF). ; EE_SOURCE_IRP_BIT for the destination pointer address must be preloaded (0=banks 0/1, 1=bank 2) ; EE_Wr_ByteCount must be loaded with the number of contiguous bytes to be copied to EEPROM (BUT DO THIS LAST). ; call WriteEEProm with any bank selected. nb: Bank 0 will be selected on WriteEEProm: ; This starts the process by initiating the first byte write. ; Subsequent byte writes are initiated after polling a set "Write Complete Interrupt Flag" (EEIF) in reg PIR2. This flag is then cleared. movf EE_Wr_ByteCount,f ; Wr Byte Count non-zero? btfsc STATUS,Z ; ; Exit before trouble! (count=0) movf Pointer_A,w ; get source address in RAM movwf EE_SourcePointer ; store in EEProm dedicated pointer movf Pointer_B,w ; get destination (addr in EEprom) bsf STATUS,RP1 ; select bank 2 movwf EEADR ; load destination address (in EEPROM) bsf STATUS,RP0 ; select bank 3 bsf EECON1,WREN ; Enable EEPROM write goto EEFirstWrite ; Do first byte write Poll_EEProm: ; Must be polled from main loop (with bank 0 selected) btfss PIR2,EEIF ; end of write cycle? ; no, bcf PIR2,EEIF ; clear EEIF flag movf EE_Wr_ByteCount,f ; More bytes to write? btfss STATUS,Z ; goto EENextWrite ; Yes, do next write ; all EEProm writes now complete

7 bsf STATUS,RP0 bcf EECON1,WREN ; Disable EEPROM write goto Bank0_Return ; all writes completed EENextWrite: ; bsf STATUS,RP1 ; bank 2 incf EEADR,f ; next EEProm Address incf EE_SourcePointer,f ; next RAM source address EEFirstWrite: decf EE_Wr_ByteCount,f ; one less byte to copy EEWrite: movf EE_SourcePointer,w movwf FSR ; set source pointer bcf STATUS,IRP btfsc GenFlags,EE_SOURCE_IRP_BIT bsf STATUS,IRP movf INDF,w ; get source data bsf STATUS,RP1 ; select bank 2 movwf EEDAT ; store data to be written bsf STATUS,RP0 ; select bank 3 bcf EECON1,EEPGD ; select EEPROM movlw 0x55 movwf EECON2 ; write 0x55 movlw 0xAA movwf EECON2 ; write 0xAA bsf EECON1,WR ; request erase/write cycle ; allow erase/write cycle to complete

8 EEPROM WRITE Prepolad: Pointer_A with start address of source data. Pointer_B with start address of destination in EEProm. GenFlags,EE_SOURCE_IRP_BIT =0 for source bank=0/1 or =1 for bank 2 EE_Wr_ByteCount with the number of bytes to copy into EEProm NB: call WriteEEProm with any selected. However: Bank 0 is selected on. NB: poll in mainllop. Bank 0 selected on entry and on. The first section of code Write_EE_Prom only executes for the first byte to be written only and does the following: Checks for zero byte count (error condition). Exits if zero. Pointer_A is copied to EE_Source_Pointer (so it can be reused by other code) Pointer_B is copied to EEADR (so it can be reused by other code) Unlock Eeprom (enable write) set EECON1,WREN EE_WriteCount is decremented Goto EE_Write Poll in the main loop:. call Poll_EEProm ; EEProm ready to write?.. Poll_EEProm checks for a write completed condition and a non-zero EE_WriteCount. If neither of these are true an immediate occurs. Poll_EEProm: Flag PIR2,EEI F is tested for completion of a previous EEprom write. If busy with a write, immediate to main loop occurs. If not busy, EE_Wr_ByteCount is tested. If count=zero, no more writes to do so: Lock the EEProm and. EEADR write address is incremented EE_WriteCount is decremented Goto EE_Write EE_Write: The EE_Source Pointer is copied to the FSR Indirect addressed data in INDF is copied to EEDAT Write one byte. (code is the same as for a single byte write.) Return (await write cycle completion)

9 Notes Sometimes it may be prudent to check the write cycle flag (EECON1) before starting a new read or write to ensure that the EEProm system is not busy still completing a write operation. In some circumstances it may be prudent to check the wrerr (write error flag in EECON1) after each write operation. Unless the device is faulty this can only occur if the write operation was curtailed for some reason. If interrupts are enabled then disable interrupts (bcf INTCON,GIE) prior to each write sequence and re-enable after the write sequence. The write sequence must be continuous.