Directives & Memory Spaces. Dr. Farid Farahmand Updated: 2/18/2019

Size: px

Start display at page:

Download "Directives & Memory Spaces. Dr. Farid Farahmand Updated: 2/18/2019"

Ronald Lesley Byrd
5 years ago
Views:

1 Directives & Memory Spaces Dr. Farid Farahmand Updated: 2/18/2019

2 Memory Types Program Memory Data Memory Stack

3 Interna PIC18 Architecture Data Memory I/O Ports 8 wires 31 x 21 Stack Memory Timers 21 wires Cock Generation 8-bit CPU 16 wires 8 wires Anaog to Digita Converter Program Memory Seria Ports Data EEPROM 8 wires Other Peripheras

4 PIC18 Memory Space

5 Program Memory Program memory addresses are 21- bit address starting at ocation 0x On-Chip Program memory or Program ROM hods the program The PROM is Fash

6 Program Memory There are three important memory ocations in the program memory. 0x0000, 0x0008, and 0x0018 caed vectors. Generay the GOTO instruction in assemby anguage is paced at a vector ocation. A vector is an address that is accessed when the reset or interrupt occurs. Vector ocations: The reset vector is 0x0000, The high priority interrupt vector is 0x0008, The ow priority interrupt vector is 0x0018.

7 Accessing Program Memory Let s Review Directives First

8 Directives Specia commands to the assember May or may not generate machine code Categories by their function Programming directives Object fie directives Contro Directives List Directives Data Directives

9 Data Directives Describe data ASCII data can be stored in memory using decare byte (DB) or DATA Program Memory

10 Accessing Program Memory Using Data Directives - Exampe DE "Test Data ; Decaring data in EEPROM

11 Accessing Program Memory Using Data Directives - Exampe Mutipe ORGs Can be used! ASCII of My Exampe of DB & DW

12 List Directives Contro isting process Exampe: LIST P=18F4520, F=INHX32 ;directive to define processor and fie format

13 Contro Directives Contro the assemby at the time of ink process #incude <P18F4520.INC> ;processor specific variabe definitions

14 ASCII TABLE

15 Data Memory Data memory is either SRAM or EEPROM. SRAM data memory begins at 12-bit address 0x000 and ends at 12-bit address 0xFFF. Not a PIC18 versions contain 4K or data memory space. Various PIC18 versions contain between 256 and 3968 bytes of data memory.

16 Data Memory There are two types of registers: genera-purpose registers (GPRs) specia-function registers (SFRs) GPRs are used to hod dynamic data when the PIC18 CPU is executing a program. SFRs are registers used by the CPU and periphera modues for controing the desired operation of the MCU. The upper 128 bytes of the data memory are used for specia function registers (SFR) at addresses 0xF80 through 0xFFF. Some versions of the PIC18 have additiona SFRs at ocations beow 0xF80.

17 Data Memory Structure

18 Data Memory (SFR Exampes) 0xFE0 0xFE8 0xFF4 0xFF3 0xFEA 0xFE9 0xFE2 0xFE1 0xFDA 0xFD9 Bank Seect Register (BSR)-4 bit Accumuator (WREG) Product High (PRODH) Product Low (PRODL) Fie Seect Register 0 High (FSR0H) Fie Seect Register 0 Low (FSR0L) Fie Seect Register 1 High (FSR1H) Fie Seect Register 1 Low (FSR1L) Fie Seect Register 2 High (FSR2H) Fie Seect Register 2 Low (FSR2L) Register Fie (Data Memory) 0xF7F 0xF7E 0xF7D 0x004 0x003 0x002 0x001 0x000 0xFD8 Status Register (SR) Program Counter (PC) Major Specia Function Registers 8-Bits 8-Bits Note: - The program counter is an interna 21-bit physica register - The program counter is modified by the GOTO, CALL, RETURN, and branch instructions. The program counter is not directy addressabe.

19 Accessing Data Memory 1. Using Direct Method (Direct Addressing) Using BSRs 2. Using Indirect Method (Indirect Addressing

20 Direct Addressing Using BSR Writing into fie registers ; BSR = 1 a=0; access bank 0x12 a=1; bank seection 0x30x2F

21 Direct Addressing A Typica Instruction showing the a-bit Op-code 8-bit data memory address a-bit a = 0 access bank a = 1 use BSR d-bit d = 0 WREG d = 1 data memory address

22 Direct Addressing Instruction Exampes MOVLW 0x06 ADDLW 0x02 MOVWF 0x00, 0 ;pace a 0x06 into W ;add a 0x02 to W ;copy W to access bank register 0x00 ; OR another version using the ACCESS keyword MOVLW 0x06 ADDLW 0x02 MOVWF 0x00, ACCESS ;pace a 0x06 into W ;add a 0x02 to W ;copy W to access bank register 0x00

23 Direct Addressing Instruction Exampes MOVLW 0x06 ;pace a 0x06 into W ADDLW 0x02 ;add a 0x02 to W MOVLB 2 ;oad BSR with bank 2 MOVWF 0x00, 1 ;copy W to data register 0x00 ;of bank 2 or address 0x200 ; OR using the BANKED keyword MOVLW 0x06 ;pace a 0x06 into W ADDLW 0x02 ;add a 0x02 to W MOVLB 2 ;oad BSR with 2 MOVWF 0x00, BANKED ;copy W to data register 0x00 ;of bank 2 or address 0x200 ; OR without any bank indication MOVLW 0x06 ;pace a 0x06 into W ADDLW 0x02 ;add a 0x02 to W MOVLB 2 ;oad BSR with bank 2 MOVWF 0x00 ;copy W to data register 0x00 ;of bank 2 or address 0x200

24 Indirect Addressing Using Fie Seect Registers (FSRs) as Pointers Memory pointer is a register that hods the address of a data register This is caed indirect addressing Easy to move/copy an entire bock Three pointer registers: FSR0, FSR1, and FSR2

25 Indirect Addressing Using Fie Seect Registers (FSRs) as Pointers Memory pointer is a register that hods the address of a data register This is caed indirect addressing Easy to move/copy an entire bock Three registers: FSR0, FSR1, and FSR2 Each FSR has a High and Low byte associated with an index Used as memory pointers to data registers Each can be used in five different formats (operands) : INDF0: Use FSR0 as pointer (index) POSTINC0: Use FSR0 as pointer and increment FSR0 POSTDEC0: Use FSR0 as pointer and decrement SR0 PREINC0: Increment FSR0 first and use as pointer PLUSW0:Add W to FSR0 and use as pointer

26 Indirect Addressing - Exampe LFSR FSR1,120 ; LOAD 12-BIT ADDRESS 120h INTO FSR1 0x0 0x0 Initiay FSR vaues are 0 and status of registers are given as above LFSR FSR1,0x0120 ; oad the LFSR FSR2,0x0150 MOVFF POSTINC1, POSTINC2 ; Load the content of eh register POINTED BY FSR1àFSR2 and THEN increment FSR1 & FSR2

27 Indirect Addressing Exampe (1) Exampes: MOVFF INDF0,INDF1 ; COPY BYTE FROM REGISTERS SHOWN BY ;FSR0 TO FSR1- NO CHANGE IN FSR ADDWF POSTINC0,1 ; ADD BYTE FROM REGISTERS SHOWN BY ;FSR0 AND W and then eave the resut in REG ; ;THEN increment FSR0 - Hence, we wi have A3 in register 0x151 after the MOVFF instruction - Note that the pointer indexes are not changing! FSR0 FSR1 A3

28 Indirect Addressing Exampe (2) Exampes: MOVFF INDF0,INDF1 ; COPY BYTE FROM REGISTERS SHOWN BY ;FSR0 TO FSR1- NO CHANGE IN FSR ADDWF POSTINC0,1 ; ADD BYTE FROM REGISTERS SHOWN BY ;FSR0 AND WàREG ; ;FSR0 IS INCREMENTED FSR0 FSR1 Assume W=2; after the ADD operation, A3+2=A5àReg 0x0121, then FSR=0x0122 0x0122 A5 A3

29 Initiaizing the RAM Appication of Indirect Addressing FSR1 0x à Set the content of the register pointed by FSR1 (0xFF) à Increment unti bit 4 is set in FSRL1 FSR1 0x What is this doing?

30 Using Tabe Pointers to Copy Data 21 bit 8-bit data registers 16 bit

31 Using Tabe Pointers Reading/writing vaues from/into the program memory one byte at a time TBLPTRU/H/L (21-bit) Word Program Memory (16-bit) TBLWT* / TBLWT*+ / TBLWT*- Tabe Latch (8-bit) Write into Memory Read from the Memory Tabe Latch (8-bit) TBLRD* / TBLRD*+ / TBLRD*-

32 Tabe Exampe Rd the register content into Tabe Latch Save in Prog Memory; Labe the vaue as BUFFER TBLPTR(U/H/L)= x Pointing to the address 0x0002 Program Memory (16-bit) TABLAT=0x02 W=0x02 REG10=0x02

33 Tabe Exampe LAB: Modify this program such that vaues 0xaa, 0xbb, 00cc stored in the program memory are copied into REG60,61,62, respectivey TBLPTR = x Pointing to the address 0x0002 Program Memory (16-bit) TABLAT=0x02 W=0x02 REG10=0x02

34 Practice Program Save your first name into EEPROM starting Register 0x20 Save your ast name into EEPROM starting Register 0x80 Save your first name into RAM starting Register 0x20 Save your ast name into RAM starting Register 0x80 Write your ast name in bank 2 starting with register 0x20 Mutipy 0x8 and 0x5 and eave the resut in registers 0x50 of the RAM in Bank 4 What is the address of the PC SFR? Load FF into RAM registers 0x30-0x40. Use Indirect addressing ony!

35 Backup

Hi Hsiao-Lung Chan Dept Electrical Engineering Chang Gung University, Taiwan

Bank Switching, Table, Macros & Modules Hi Hsiao-Lung Chan Dept Electrical Engineering Chang Gung University, Taiwan chanhl@mail.cgu.edu.twcgu PIC18 memory access up to 2 MB of program memory Inside the