Introduction to Digital Logic
|
|
- Brett Holland
- 6 years ago
- Views:
Transcription
1 Introduction to Digital Logic Lecture 5 Simple CPU Overview Instruction Set
2 Software Process Software Program High Level Language Description if (x > ) x = x + y - z; a = b*x; Compiler JLEZ X,SKIP MOVE.W X,D ADD CMPI.W X,X,Y #,D SUB BLE X,X,Z SKIP SKIP: MUL ADD A,B,X Y,D SUB Z,D SKIP MUL Assembler Program Executing Mark Redekopp, All rights reserved.c/.cpp files Loader / OS Assembly (.asm/.s files) A compiler (i.e. gcc, VisualC++, etc.) also includes the assembler & linker Executable Binary Image Object/Machine Code (.o files) Linker
3 Hardware Components Computer hardware can be classified into three categories Input/Output Devices Supplies and consumes data Supplies the program Keyboard, Mouse, Monitor, Hard Drive (RAM/ROM) Temporary storage for data and program Performs operations on data as indicated by SW program Pentium, Celeron, etc. Input Devices Software Program Output Devices
4 Like the memories we learned about earlier Set of cells/rows that each store a group of bits (usually, byte = 8 bits) but can be larger like -bytes = 6-bits, or even -bytes = -bits, etc. Unique address assigned to each cell/row Used to reference the value in that location Address 5 FF 6 Device
5 Operations Memories perform operations Read: retrieves data value in a particular location (specified using the address) Write: changes data in a location to a new value To perform these operations a set of address, data, and control inputs/outputs are used Note: A group of wires/signals is referred to as a bus Thus, we say that memories have an address, data, and control bus. Read 5 Write Addr. 5 A Read Operation Addr. 5 Mark Redekopp, All rights reserved A Write Operation
6 Address Performs the same -step process over and over again Fetch an instruction from memory Decode/ the instruction Generate necessary control signals to control the datapath to execute the given instruction Execute the instruction Perform the specified operation These steps are known as the Instruction Cycle Fetch Instruction Arithmetic Circuitry Circuitry ADD SUB CMP Add the specified values Generate control signals
7 Primary Components of a ALU Registers Circuitry Connects to memory and I/O via address, data, and control buses Addr 5 6
8 Arithmetic and Logic Unit (ALU) Executes arithmetic operations like addition and subtraction along with logical operations (AND, OR, etc.) out op. ALU ADD, SUB, AND, OR in in Addr 5 6
9 Registers Some are for general use by software Registers provide fast, temporary storage locations within the processor (to avoid having to read/write slow memory) Others are required for specific purposes to ensure proper operation of the hardware out op. ALU ADD, SUB, AND, OR in in R-RF PC Addr 5 6
10 General Purpose Registers Registers available to software instructions for use by the programmer/compiler Instructions use these registers as inputs (source locations) and outputs (destination locations) out op. ALU ADD, SUB, AND, OR in in R-RF PC Addr 5 6
11 What if we didn t have registers? Example w/o registers: F = (X+Y) (X*Y) Requires an ADD instruction, MULtiply instruction, and SUBtract Instruction w/o registers ADD: Load X and Y from memory, store result to memory MUL: Load X and Y again from mem., store result to mem. SUB: Load results from ADD and MUL and store result to mem 9 memory accesses out op. ALU ADD, SUB, AND, OR in in R-RF PC Addr 5 6 X Y F
12 What if we have registers? Example w/ registers: F = (X+Y) (X*Y) Load X and Y into registers ADD: R + R and store result in R MUL: R * R and store result in R SUB: R R and store result in R Store R back to memory total memory access out op. ALU ADD, SUB, AND, OR in in R-RF PC X Y Addr 5 6 X Y F
13 Other Registers Some bookkeeping information is needed to make the processor operate correctly Example: Program Counter (PC) Recall that the processor must fetch instructions from memory before decoding and executing them PC register holds the address of the currently executing instruction out op. ALU ADD, SUB, AND, OR in in R-RF PC Addr 5 6
14 Fetching an Instruction To fetch an instruction Assume instructions are stored in a 56x6 bit memory (each instruction is stored using a -byte / 6-bit value PC contains the address of the instruction The value in the PC is placed on the address bus and the memory is told to read The PC is incremented, and the process is repeated for the next instruction out op. ALU ADD, SUB, AND, OR in in R-RF PC PC = Addr = Addr = inst. machine code = Read FF inst. inst. inst. inst. inst. 5
15 Fetching an Instruction To fetch an instruction Assume instructions are stored in a 56x6 bit memory (each instruction is stored using a -byte / 6-bit value PC contains the address of the instruction The value in the PC is placed on the address bus and the memory is told to read The PC is incremented, and the process is repeated for the next instruction out op. ALU ADD, SUB, AND, OR in in R-RF PC PC = Addr = Addr = inst. machine code = Read FF inst. inst. inst. inst. inst. 5
16 Circuitry circuitry is used to decode the instruction and then generate the necessary signals to complete its execution s the ALU Selects Registers to be used as source and destination locations out op. ALU ADD, SUB, AND, OR in in R-R PC Addr FF inst. inst. inst. inst. inst. 5
17 Circuitry Assume hex is machine code for an ADD instruction of R = R + R Logic will select the registers (R and R) tell the ALU to add select the destination register (R) ADD PC Addr inst. out ALU ADD in in R-RF FF inst. inst. inst. 5
18 Input / Output Keyboard, Mouse, Display, USB devices, Hard Drive, Printer, etc. can perform reads and writes on I/O devices just as it does on memory I/O devices have locations that contain data that the processor can access These locations are assigned unique addresses just like memory 7F a = 6 hex in ASCII Keyboard Interface 8 A D C READ
19 Input / Output Writing a value to the video adapter can set a pixel on the screen 7F Video Adapter A D C FE may signify a white dot at a particular location FE 6 FE WRITE Keyboard Interface 8 6
20 Our 8-bit Computer 8-bit data and addresses but 6-bit instructions I/O 8-bit input data from keyboard 8 LED s for output display Store program instructions For our design we ll use a separate 56x6 instruction memory (56 rows / instructions each being 6-bits) Stores program data For our design we ll use a separate 8x8 data memory (each data element is a byte-size value Registers Temporary storage locations inside processor for fast access For our design we ll use (6) 8-bit registers: R-RF
21 Address Space With 8-bit values we can make 56 unique addresses Mark Redekopp, All rights reserved Address range: -FF hex We said our data memory will only have 8 locations Address range: 7F hex What about the other 8? We will map our I/O devices to some of those unused addresses Read of address 8 hex will return keyboard data Write of address 8 hex will output to LED s 7F 8 FF Keyboard (Read) / LEDs (Write) 8 Unoccupied / Unused 8 x 8 RAM I/O and Unused Space
22 Instruction Set supports instructions Instruction Type Comment ADD Rd,Rs,Rt Rd = Rs + Rt SUB Rd,Rs,Rt Rd = Rs Rt MOVE Rd,Rs Rd = Rs XOR Rd,Rs,Rt Rd = Rs XOR Rt AND Rd,Rs,Rt Rd = Rs AND Rt OR Rd,Rs,Rt Rd = Rs OR Rt JEQZ Rt,WX If(Rt = ) jump to instruc. At address WX JLTZ Rt,WX If(Rt < ) jump to instruc. At address WX ST Rs,[Rt] Store to (MEM[Rt] = Rs) LDC Rd,XY Load Constant (Rd = XY) LD Rd,[Rt] Load from (Rd = MEM[Rt] )
23 Machine Code Form of Instructions Every instruction is represented by a 6-bit binary string: IW[5:] Basic Machine Code Format broken into four - bit fields of info Opcode: -bit field indicating what instruction it is d/w: d = Dest. register number or W: Upper -bits of jump address s/x: s = Operand A reg. number or X: Lower -bits of jump address or upper -bits of constant for load t/y: t = Operand B reg. number of Y: Lower -bits of constant for load
24 Machine Code Form of Instructions Mark Redekopp, All rights reserved IW[5:] IW[:8] IW[7:] IW[:] ADD d s t SUB d s t MOVE d s XOR d s t AND 5 d s t OR 6 d s t JEQZ 8 W X t JLTZ 9 W X t ST B s t LDC E d X Y LD F d t Examples: ADD R,R5,R6 => 56 hex; MOVE RC,R => c; JEQZ R,C => 8C hex; LDC R,FE => EFE; LD R7,[R] => F7;
25 Conditional (If) Example if(x==y) Z = X+Y Else Z = X; IMEM Addr Instruction Type Comment LDC R, Load constant for later use LDC R,8 Address of Keyboard Input LD R,[R] Read in X value from keyboard LD R,[R] Read in Y value from keyboard SUB R,R,R Do X-Y to check if X==Y 5 JEQZ R,8 Goto THEN portion 6 MOVE R5,R Z = X 7 JEQZ R,9 Skip the THEN portion 8 ADD R5,R,R Z = X + Y 9 ST R5,[R] Write value to LED s A next instruction
26 Loop Example char data[] = { }; int i, j=; for(i=9; i >= ; i--) j = j + data[i]; IMEM Addr Instruction Type Comment LDC R, Constant for later use LDC R, Constant for Decrement Op. LDC R, Based address of data array LDC R, J = LDC R,9 I = 9 5 JLTZ R,B I >=? 6 ADD R5,R,R Setup address to data[i] 7 LD R6,[R5] Get value of data[i] 8 ADD R,R,R6 J = j + data[i] 9 SUB R,R,R I-- A JEQZ R,5 Repeat B next instruction
Introduction to Digital Logic
Introduction to Digital Logic Lecture 26 Simple CPU HW Design Our 8-bit Computer 8-bit data and addresses but 16-bit instructions I/O 8-bit input data from keyboard 8 LED s for output display Memory Store
More information16.1. Unit 16. Computer Organization Design of a Simple Processor
6. Unit 6 Computer Organization Design of a Simple Processor HW SW 6.2 You Can Do That Cloud & Distributed Computing (CyberPhysical, Databases, Data Mining,etc.) Applications (AI, Robotics, Graphics, Mobile)
More informationEE 109 Unit 12 Computer Organization
1 EE 19 Unit 12 Computer Organization 2 Review of some key concepts from the first half of the semester A BRIEF SUMMARY 3 A Few Big Ideas 1 Setting and clearing bits in a register tells the hardware what
More informationEE 457. EE 457 Unit 0. Prerequisites. Course Info Lecture: Prof. Redekopp Class Introduction Basic Hardware Organization
0.1 0.2 EE 457 EE 457 Unit 0 Class Introduction Basic Hardware Organization Focus on CPU Design Microarchitecture General Digital System Design Focus on Hierarchy Cache Virtual Focus on Computer Arithmetic
More informationComputer Architecture 2/26/01 Lecture #
Computer Architecture 2/26/01 Lecture #9 16.070 On a previous lecture, we discussed the software development process and in particular, the development of a software architecture Recall the output of the
More informationEE 109 Unit 12 Computer Organization. A Few Big Ideas 1. A Few Big Ideas 2 A BRIEF SUMMARY. Clocking or enables are necessary to say
EE 9 Unit Computer Organization Review of some key concepts from the first half of the semester and revisit what CECS prepares you to do in the future. A BRIEF SUMMARY A Few Big Ideas bits in a register
More informationMark Redekopp, All rights reserved. EE 352 Unit 4. Assembly and the MARS Simulator Control Flow (Branch Instructions)
EE 352 Unit 4 Assembly and the MARS Simulator Control Flow (Branch Instructions) Directives Pseudo-instructions ASSEMBLERS Assembler Syntax In MARS and most assemblers each line of the assembly program
More informationMark Redekopp and Gandhi Puvvada, All rights reserved. EE 357 Unit 15. Single-Cycle CPU Datapath and Control
EE 37 Unit Single-Cycle CPU path and Control CPU Organization Scope We will build a CPU to implement our subset of the MIPS ISA Memory Reference Instructions: Load Word (LW) Store Word (SW) Arithmetic
More informationCS3350B Computer Architecture Winter 2015
CS3350B Computer Architecture Winter 2015 Lecture 5.5: Single-Cycle CPU Datapath Design Marc Moreno Maza www.csd.uwo.ca/courses/cs3350b [Adapted from lectures on Computer Organization and Design, Patterson
More informationEECS150 - Digital Design Lecture 10- CPU Microarchitecture. Processor Microarchitecture Introduction
EECS150 - Digital Design Lecture 10- CPU Microarchitecture Feb 18, 2010 John Wawrzynek Spring 2010 EECS150 - Lec10-cpu Page 1 Processor Microarchitecture Introduction Microarchitecture: how to implement
More informationThe MIPS Instruction Set Architecture
The MIPS Set Architecture CPS 14 Lecture 5 Today s Lecture Admin HW #1 is due HW #2 assigned Outline Review A specific ISA, we ll use it throughout semester, very similar to the NiosII ISA (we will use
More informationEECS150 - Digital Design Lecture 9- CPU Microarchitecture. Watson: Jeopardy-playing Computer
EECS150 - Digital Design Lecture 9- CPU Microarchitecture Feb 15, 2011 John Wawrzynek Spring 2011 EECS150 - Lec09-cpu Page 1 Watson: Jeopardy-playing Computer Watson is made up of a cluster of ninety IBM
More informationCS 61C: Great Ideas in Computer Architecture Datapath. Instructors: John Wawrzynek & Vladimir Stojanovic
CS 61C: Great Ideas in Computer Architecture Datapath Instructors: John Wawrzynek & Vladimir Stojanovic http://inst.eecs.berkeley.edu/~cs61c/fa15 1 Components of a Computer Processor Control Enable? Read/Write
More informationComputer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: MIPS Instruction Set Architecture
Computer Science 324 Computer Architecture Mount Holyoke College Fall 2009 Topic Notes: MIPS Instruction Set Architecture vonneumann Architecture Modern computers use the vonneumann architecture. Idea:
More information11. A Computing Machine
COMPUTER SCIENCE S E D G E W I C K / W A Y N E Computer Science Including Programming in Java 11. A Computing Machine Section 5.1 http://introcs.cs.princeton.edu COMPUTER SCIENCE S E D G E W I C K / W
More informationCS 101, Mock Computer Architecture
CS 101, Mock Computer Architecture Computer organization and architecture refers to the actual hardware used to construct the computer, and the way that the hardware operates both physically and logically
More informationReview. N-bit adder-subtractor done using N 1- bit adders with XOR gates on input. Lecture #19 Designing a Single-Cycle CPU
CS6C L9 CPU Design : Designing a Single-Cycle CPU () insteecsberkeleyedu/~cs6c CS6C : Machine Structures Lecture #9 Designing a Single-Cycle CPU 27-7-26 Scott Beamer Instructor AI Focuses on Poker Review
More informationBASIC COMPUTER ORGANIZATION. Operating System Concepts 8 th Edition
BASIC COMPUTER ORGANIZATION Silberschatz, Galvin and Gagne 2009 Topics CPU Structure Registers Memory Hierarchy (L1/L2/L3/RAM) Machine Language Assembly Language Running Process 3.2 Silberschatz, Galvin
More informationECE232: Hardware Organization and Design. Computer Organization - Previously covered
ECE232: Hardware Organization and Design Part 6: MIPS Instructions II http://www.ecs.umass.edu/ece/ece232/ Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Computer Organization
More informationMark Redekopp, All rights reserved. EE 357 Unit 11 MIPS ISA
EE 357 Unit 11 MIPS ISA Components of an ISA 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support SUBtract instruc. vs. NEGate + ADD instrucs. 3. Registers accessible
More informationCS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #18 Introduction to CPU Design 2007-7-25 Scott Beamer, Instructor CS61C L18 Introduction to CPU Design (1) What about overflow? Consider
More informationCS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #19 Designing a Single-Cycle CPU 27-7-26 Scott Beamer Instructor AI Focuses on Poker CS61C L19 CPU Design : Designing a Single-Cycle CPU
More information18. Machine Language. Computer Systems. COMP1917: Computing 1. Machine Language Programming. History of Computer Technology
COMP1917 13s2 18. Machine Language 1 COMP1917: Computing 1 18. Machine Language Computer Systems Recall: modern computer systems are layered. Applications Programming Language Operating System Assembly
More information17.1. Unit 17. Instruction Sets Picoblaze Processor
17.1 Unit 17 Instruction Sets Picoblaze Processor INSTRUCTION SET OVERVIEW 17.2 17.3 Instruction Set Review Defines the software interface of the processor and memory system Instruction set is the vocabulary
More informationComputer Science 61C Spring Friedland and Weaver. The MIPS Datapath
The MIPS Datapath 1 The Critical Path and Circuit Timing The critical path is the slowest path through the circuit For a synchronous circuit, the clock cycle must be longer than the critical path otherwise
More informationChapter 4. The Processor. Computer Architecture and IC Design Lab
Chapter 4 The Processor Introduction CPU performance factors CPI Clock Cycle Time Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS
More informationUC Berkeley CS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c UC Berkeley CS61C : Machine Structures Lecture 25 CPU Design: Designing a Single-cycle CPU Lecturer SOE Dan Garcia www.cs.berkeley.edu/~ddgarcia T-Mobile s Wi-Fi / Cell phone
More informationTopic Notes: MIPS Instruction Set Architecture
Computer Science 220 Assembly Language & Comp. Architecture Siena College Fall 2011 Topic Notes: MIPS Instruction Set Architecture vonneumann Architecture Modern computers use the vonneumann architecture.
More informationComputer Architecture /
Computer Architecture 02-201 / 02-601 The Conceptual Architecture of a Computer PC CPU register 0 register 1 register 2 registers hold small amounts of data for processing by the CPU Reading / writing
More informationCOSC 122 Computer Fluency. Computer Organization. Dr. Ramon Lawrence University of British Columbia Okanagan
COSC 122 Computer Fluency Computer Organization Dr. Ramon Lawrence University of British Columbia Okanagan ramon.lawrence@ubc.ca Key Points 1) The standard computer (von Neumann) architecture consists
More informationCOSC 6385 Computer Architecture. Instruction Set Architectures
COSC 6385 Computer Architecture Instruction Set Architectures Spring 2012 Instruction Set Architecture (ISA) Definition on Wikipedia: Part of the Computer Architecture related to programming Defines set
More informationEE 109 Unit 10 Assembler Directives and Control Flow
1 EE 109 Unit 10 Assembler Directives and Control Flow 2 Directives Pseudo-instructions ASSEMBLERS 3 Writing Assembly Code written at the assembly level needs some additional help for specifying certain
More informationProcessor (I) - datapath & control. Hwansoo Han
Processor (I) - datapath & control Hwansoo Han Introduction CPU performance factors Instruction count - Determined by ISA and compiler CPI and Cycle time - Determined by CPU hardware We will examine two
More informationinst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 18 CPU Design: The Single-Cycle I ! Nasty new windows vulnerability!
inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 18 CPU Design: The Single-Cycle I CS61C L18 CPU Design: The Single-Cycle I (1)! 2010-07-21!!!Instructor Paul Pearce! Nasty new windows vulnerability!
More informationUnit 17. Instruction Set Review INSTRUCTION SET OVERVIEW. Historical Instruction Format Options. Instruction Sets Picoblaze Processor
17.1 17.2 Unit 17 Instruction Sets Picoblaze Processor INSTRUCTION SET OVERVIEW 17.3 17.4 Instruction Set Review Defines the software interface of the processor and memory system Instruction set is the
More informationInstruction Set Architecture. "Speaking with the computer"
Instruction Set Architecture "Speaking with the computer" The Instruction Set Architecture Application Compiler Instr. Set Proc. Operating System I/O system Instruction Set Architecture Digital Design
More informationLecture 2: The Instruction Set Architecture
Lecture 2: The Instruction Set Architecture COS / ELE 375 Computer Architecture and Organization Princeton University Fall 2015 Prof. David August 1 2 Quiz 0 3 Quiz 0 CD 3 Miles of Music 4 Pits and Lands
More informationAnnouncements HW1 is due on this Friday (Sept 12th) Appendix A is very helpful to HW1. Check out system calls
Announcements HW1 is due on this Friday (Sept 12 th ) Appendix A is very helpful to HW1. Check out system calls on Page A-48. Ask TA (Liquan chen: liquan@ece.rutgers.edu) about homework related questions.
More informationare Softw Instruction Set Architecture Microarchitecture are rdw
Program, Application Software Programming Language Compiler/Interpreter Operating System Instruction Set Architecture Hardware Microarchitecture Digital Logic Devices (transistors, etc.) Solid-State Physics
More informationDigital System Design Using Verilog. - Processing Unit Design
Digital System Design Using Verilog - Processing Unit Design 1.1 CPU BASICS A typical CPU has three major components: (1) Register set, (2) Arithmetic logic unit (ALU), and (3) Control unit (CU) The register
More informationELEC 5200/6200 Computer Architecture and Design Spring 2017 Lecture 4: Datapath and Control
ELEC 52/62 Computer Architecture and Design Spring 217 Lecture 4: Datapath and Control Ujjwal Guin, Assistant Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849
More informationFaculty of Science FINAL EXAMINATION
Faculty of Science FINAL EXAMINATION COMPUTER SCIENCE COMP 273 INTRODUCTION TO COMPUTER SYSTEMS Examiner: Prof. Michael Langer April 18, 2012 Associate Examiner: Mr. Joseph Vybihal 2 P.M. 5 P.M. STUDENT
More informationECE 2300 Digital Logic & Computer Organization. More Single Cycle Microprocessor
ECE 23 Digital Logic & Computer Organization Spring 28 More Single Cycle Microprocessor Lecture 6: HW6 due tomorrow Announcements Prelim 2: Tues April 7, 7:3pm, Phillips Hall Coverage: Lectures 8~6 Inform
More informationECE260: Fundamentals of Computer Engineering
Datapath for a Simplified Processor James Moscola Dept. of Engineering & Computer Science York College of Pennsylvania Based on Computer Organization and Design, 5th Edition by Patterson & Hennessy Introduction
More informationCOMPUTER ORGANIZATION
COMPUTER ORGANIZATION INDEX UNIT-II PPT SLIDES Srl. No. Module as per Session planner Lecture No. PPT Slide No. 1. Register Transfer language 2. Register Transfer Bus and memory transfers 3. Arithmetic
More informationUC Berkeley CS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c UC Berkeley CS61C : Machine Structures Lecture 24 Introduction to CPU Design 2007-03-14 CS61C L24 Introduction to CPU Design (1) Lecturer SOE Dan Garcia www.cs.berkeley.edu/~ddgarcia
More informationClever Signed Adder/Subtractor. Five Components of a Computer. The CPU. Stages of the Datapath (1/5) Stages of the Datapath : Overview
Lecturer SOE Dan Garcia inst.eecs.berkeley.edu/~cs61c UCB CS61C : Machine Structures Lecture 24 Introduction to CPU design Hi to Vitaly Babiy from Albany, NY! 2008-03-21 Stanford researchers developing
More informationCENG3420 Lecture 03 Review
CENG3420 Lecture 03 Review Bei Yu byu@cse.cuhk.edu.hk 2017 Spring 1 / 38 CISC vs. RISC Complex Instruction Set Computer (CISC) Lots of instructions of variable size, very memory optimal, typically less
More informationComputer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: MIPS Instruction Set Architecture
Computer Science 324 Computer Architecture Mount Holyoke College Fall 2007 Topic Notes: MIPS Instruction Set Architecture vonneumann Architecture Modern computers use the vonneumann architecture. Idea:
More informationEC-801 Advanced Computer Architecture
EC-801 Advanced Computer Architecture Lecture 5 Instruction Set Architecture I Dr Hashim Ali Fall 2018 Department of Computer Science and Engineering HITEC University Taxila!1 Instruction Set Architecture
More informationMath 230 Assembly Programming (AKA Computer Organization) Spring MIPS Intro
Math 230 Assembly Programming (AKA Computer Organization) Spring 2008 MIPS Intro Adapted from slides developed for: Mary J. Irwin PSU CSE331 Dave Patterson s UCB CS152 M230 L09.1 Smith Spring 2008 MIPS
More informationCISC 662 Graduate Computer Architecture. Lecture 4 - ISA MIPS ISA. In a CPU. (vonneumann) Processor Organization
CISC 662 Graduate Computer Architecture Lecture 4 - ISA MIPS ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,
More informationECE331: Hardware Organization and Design
ECE331: Hardware Organization and Design Lecture 35: Final Exam Review Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Material from Earlier in the Semester Throughput and latency
More informationEE 3170 Microcontroller Applications
EE 3170 Microcontroller Applications Lecture 4 : Processors, Computers, and Controllers - 1.2 (reading assignment), 1.3-1.5 Based on slides for ECE3170 by Profs. Kieckhafer, Davis, Tan, and Cischke Outline
More informationLaboratory 5 Processor Datapath
Laboratory 5 Processor Datapath Description of HW Instruction Set Architecture 16 bit data bus 8 bit address bus Starting address of every program = 0 (PC initialized to 0 by a reset to begin execution)
More informationCpE242 Computer Architecture and Engineering Designing a Single Cycle Datapath
CpE242 Computer Architecture and Engineering Designing a Single Cycle Datapath CPE 442 single-cycle datapath.1 Outline of Today s Lecture Recap and Introduction Where are we with respect to the BIG picture?
More information361 datapath.1. Computer Architecture EECS 361 Lecture 8: Designing a Single Cycle Datapath
361 datapath.1 Computer Architecture EECS 361 Lecture 8: Designing a Single Cycle Datapath Outline of Today s Lecture Introduction Where are we with respect to the BIG picture? Questions and Administrative
More informationCISC 662 Graduate Computer Architecture. Lecture 4 - ISA
CISC 662 Graduate Computer Architecture Lecture 4 - ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,
More informationMIPS ISA. 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support
Components of an ISA EE 357 Unit 11 MIPS ISA 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support SUBtract instruc. vs. NEGate + ADD instrucs. 3. Registers accessible
More informationEXPERIMENT NO. 1 THE MKT 8085 MICROPROCESSOR TRAINER
OBJECT: EXPERIMENT NO. 1 THE MKT 8085 MICROPROCESSOR TRAINER To understand the structure and operating instruction of the microprocessor trainer. INTRODUCTION: The MKT 8085 is a single-board microcomputer,
More informationProcessor. Han Wang CS3410, Spring 2012 Computer Science Cornell University. See P&H Chapter , 4.1 4
Processor Han Wang CS3410, Spring 2012 Computer Science Cornell University See P&H Chapter 2.16 20, 4.1 4 Announcements Project 1 Available Design Document due in one week. Final Design due in three weeks.
More informationCC411: Introduction To Microprocessors
CC411: Introduction To Microprocessors OBJECTIVES this chapter enables the student to: Use number { base 2, base 10, or base 16 }. Add and subtract binary/hex numbers. Represent any binary number in 2
More informationCOSC121: Computer Systems: Review
COSC121: Computer Systems: Review Jeremy Bolton, PhD Assistant Teaching Professor Constructed using materials: - Patt and Patel Introduction to Computing Systems (2nd) - Patterson and Hennessy Computer
More informationMark Redekopp, All rights reserved. EE 357 Unit 5. Assembler Directives and Programming
EE 357 Unit 5 Assembler Directives and Programming Assembler Syntax An assembler takes a source code file and builds a memory image (binary) executable file Specifies the location in memory (either relative
More informationMath 230 Assembly Programming (AKA Computer Organization) Spring 2008
Math 230 Assembly Programming (AKA Computer Organization) Spring 2008 MIPS Intro II Lect 10 Feb 15, 2008 Adapted from slides developed for: Mary J. Irwin PSU CSE331 Dave Patterson s UCB CS152 M230 L10.1
More informationCPE 335 Computer Organization. Basic MIPS Architecture Part I
CPE 335 Computer Organization Basic MIPS Architecture Part I Dr. Iyad Jafar Adapted from Dr. Gheith Abandah slides http://www.abandah.com/gheith/courses/cpe335_s8/index.html CPE232 Basic MIPS Architecture
More informationComputer Organization MIPS ISA
CPE 335 Computer Organization MIPS ISA Dr. Iyad Jafar Adapted from Dr. Gheith Abandah Slides http://www.abandah.com/gheith/courses/cpe335_s08/index.html CPE 232 MIPS ISA 1 (vonneumann) Processor Organization
More informationISA and RISCV. CASS 2018 Lavanya Ramapantulu
ISA and RISCV CASS 2018 Lavanya Ramapantulu Program Program =?? Algorithm + Data Structures Niklaus Wirth Program (Abstraction) of processor/hardware that executes 3-Jul-18 CASS18 - ISA and RISCV 2 Program
More informationCS 265. Computer Architecture. Wei Lu, Ph.D., P.Eng.
CS 265 Computer Architecture Wei Lu, Ph.D., P.Eng. Part 3: von Neumann Architecture von Neumann Architecture Our goal: understand the basics of von Neumann architecture, including memory, control unit
More informationMicrocontroller Systems
µcontroller systems 1 / 43 Microcontroller Systems Engineering Science 2nd year A2 Lectures Prof David Murray david.murray@eng.ox.ac.uk www.robots.ox.ac.uk/ dwm/courses/2co Michaelmas 2014 µcontroller
More informationChapter 4 The Processor 1. Chapter 4A. The Processor
Chapter 4 The Processor 1 Chapter 4A The Processor Chapter 4 The Processor 2 Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware
More informationCS 61C: Great Ideas in Computer Architecture. MIPS CPU Datapath, Control Introduction
CS 61C: Great Ideas in Computer Architecture MIPS CPU Datapath, Control Introduction Instructor: Alan Christopher 7/28/214 Summer 214 -- Lecture #2 1 Review of Last Lecture Critical path constrains clock
More informationComputers and Microprocessors. Lecture 34 PHYS3360/AEP3630
Computers and Microprocessors Lecture 34 PHYS3360/AEP3630 1 Contents Computer architecture / experiment control Microprocessor organization Basic computer components Memory modes for x86 series of microprocessors
More informationA Processor. Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University. See: P&H Chapter , 4.1-3
A Processor Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University See: P&H Chapter 2.16-20, 4.1-3 Let s build a MIPS CPU but using Harvard architecture Basic Computer System Registers ALU
More informationVirtual machines. Virtual machines. Abstractions for computers. Abstractions for computers. Virtual machines
1 2 Problems with programming using machine code Difficult to remember instructions Difficult to remember variables Hard to calculate addresses/relocate variables or functions Need to handle instruction
More informationComputer Organization. Structure of a Computer. Registers. Register Transfer. Register Files. Memories
Computer Organization Structure of a Computer Computer design as an application of digital logic design procedures Computer = processing unit + memory system Processing unit = control + Control = finite
More informationEE 109 Unit 10 MIPS Instruction Set. MIPS Processor and Bus Interface. Instruction Set Architecture (ISA) MIPS INSTRUCTION OVERVIEW
10.1 10.2 EE 109 Unit 10 MIPS Instruction Set MIPS INSTRUCTION OVERVIEW 10.3 10.4 Instruction Set Architecture (ISA) Defines the of the processor and memory system Instruction set is the the HW can understand
More informationCS 31: Intro to Systems Digital Logic. Kevin Webb Swarthmore College February 2, 2016
CS 31: Intro to Systems Digital Logic Kevin Webb Swarthmore College February 2, 2016 Reading Quiz Today Hardware basics Machine memory models Digital signals Logic gates Circuits: Borrow some paper if
More informationData Manipulation. Chih-Wei Tang ( 唐之瑋 ) Department of Communication Engineering National Central University JhongLi, Taiwan
Data Manipulation Chih-Wei Tang ( 唐之瑋 ) Department of Communication Engineering National Central University JhongLi, Taiwan Outline Computer Architecture Machine Language Program Execution Arithmetic/Logic
More informationCS 61C: Great Ideas in Computer Architecture (Machine Structures) Lecture 28: Single- Cycle CPU Datapath Control Part 1
CS 61C: Great Ideas in Computer Architecture (Machine Structures) Lecture 28: Single- Cycle CPU Datapath Control Part 1 Guest Lecturer: Sagar Karandikar hfp://inst.eecs.berkeley.edu/~cs61c/ http://research.microsoft.com/apps/pubs/default.aspx?id=212001!
More informationEECS 151/251A Fall 2017 Digital Design and Integrated Circuits. Instructor: John Wawrzynek and Nicholas Weaver. Lecture 13 EE141
EECS 151/251A Fall 2017 Digital Design and Integrated Circuits Instructor: John Wawrzynek and Nicholas Weaver Lecture 13 Project Introduction You will design and optimize a RISC-V processor Phase 1: Design
More informationStored Program Concept. Instructions: Characteristics of Instruction Set. Architecture Specification. Example of multiple operands
Stored Program Concept Instructions: Instructions are bits Programs are stored in memory to be read or written just like data Processor Memory memory for data, programs, compilers, editors, etc. Fetch
More informationCOMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 4. The Processor
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle
More informationCPU Structure and Function
Computer Architecture Computer Architecture Prof. Dr. Nizamettin AYDIN naydin@yildiz.edu.tr nizamettinaydin@gmail.com http://www.yildiz.edu.tr/~naydin CPU Structure and Function 1 2 CPU Structure Registers
More informationChapter 4. The Processor
Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations A simplified
More informationUNIT:2 BASIC COMPUTER ORGANIZATION AND DESIGN
1 UNIT:2 BASIC COMPUTER ORGANIZATION AND DESIGN BASIC COMPUTER ORGANIZATION AND DESIGN 2.1 Instruction Codes 2.2 Computer Registers AC or Accumulator, Data Register or DR, the AR or Address Register, program
More informationMark Redekopp, All rights reserved. EE 352 Unit 3 MIPS ISA
EE 352 Unit 3 MIPS ISA Instruction Set Architecture (ISA) Defines the software interface of the processor and memory system Instruction set is the vocabulary the HW can understand and the SW is composed
More informationIntroduction to Computers & Programming
16.070 Introduction to Computers & Programming Computer Architecture, Machine Language, Program Execution Prof. Kristina Lundqvist Dept. of Aero/Astro, MIT Chapter Summary This chapter introduces the activities
More informationLecture 12: Single-Cycle Control Unit. Spring 2018 Jason Tang
Lecture 12: Single-Cycle Control Unit Spring 2018 Jason Tang 1 Topics Control unit design Single cycle processor Control unit circuit implementation 2 Computer Organization Computer Processor Memory Devices
More information2.2 THE MARIE Instruction Set Architecture
2.2 THE MARIE Instruction Set Architecture MARIE has a very simple, yet powerful, instruction set. The instruction set architecture (ISA) of a machine specifies the instructions that the computer can perform
More informationComputer Organization CS 206 T Lec# 2: Instruction Sets
Computer Organization CS 206 T Lec# 2: Instruction Sets Topics What is an instruction set Elements of instruction Instruction Format Instruction types Types of operations Types of operand Addressing mode
More informationComputer Organization (Autonomous)
Computer Organization (Autonomous) UNIT II Sections - A & D Prepared by Anil Kumar Prathipati, Asst. Prof., Dept. of CSE. SYLLABUS Basic Computer Organization and Design: Instruction codes Stored Program
More informationBASIC COMPUTER ORGANIZATION AND DESIGN
1 BASIC COMPUTER ORGANIZATION AND DESIGN Instruction Codes Computer Registers Computer Instructions Timing and Control Instruction Cycle Memory Reference Instructions Input-Output and Interrupt Complete
More informationDesign of Digital Circuits 2017 Srdjan Capkun Onur Mutlu (Guest starring: Frank K. Gürkaynak and Aanjhan Ranganathan)
Microarchitecture Design of Digital Circuits 27 Srdjan Capkun Onur Mutlu (Guest starring: Frank K. Gürkaynak and Aanjhan Ranganathan) http://www.syssec.ethz.ch/education/digitaltechnik_7 Adapted from Digital
More informationComputer Organization II CMSC 3833 Lecture 33
Term MARIE Definition Machine Architecture that is Really Intuitive and Easy 4.8.1 The Architecture Figure s Architecture Characteristics: Binary, two s complement Stored program, fixed word length Word
More informationLecture 4: MIPS Instruction Set
Lecture 4: MIPS Instruction Set No class on Tuesday Today s topic: MIPS instructions Code examples 1 Instruction Set Understanding the language of the hardware is key to understanding the hardware/software
More informationChapter 2. Instructions: Language of the Computer. Adapted by Paulo Lopes
Chapter 2 Instructions: Language of the Computer Adapted by Paulo Lopes Instruction Set The repertoire of instructions of a computer Different computers have different instruction sets But with many aspects
More informationCS 31: Intro to Systems Digital Logic. Kevin Webb Swarthmore College February 3, 2015
CS 31: Intro to Systems Digital Logic Kevin Webb Swarthmore College February 3, 2015 Reading Quiz Today Hardware basics Machine memory models Digital signals Logic gates Circuits: Borrow some paper if
More informationThe Processor. Z. Jerry Shi Department of Computer Science and Engineering University of Connecticut. CSE3666: Introduction to Computer Architecture
The Processor Z. Jerry Shi Department of Computer Science and Engineering University of Connecticut CSE3666: Introduction to Computer Architecture Introduction CPU performance factors Instruction count
More information1a Computers, Problem Solving!
1a Computers, Problem Solving!! 1E3! 1a Computers and Problem Solving 1 Objectives! n To introduce the architecture of a computer.! n To introduce the notion of a programming language.! n To explore computational
More information