16.1. Unit 16. Computer Organization Design of a Simple Processor

Transcription

1 6. Unit 6 Computer Organization Design of a Simple Processor

2 HW SW 6.2 You Can Do That Cloud & Distributed Computing (CyberPhysical, Databases, Data Mining,etc.) Applications (AI, Robotics, Graphics, Mobile) Scripting & Interfaces C / C++ / Java Networked Applications Applications Systems & Networking (Embedded Systems, Networks) Assembly / Machine Code OS Libraries Architecture (Processor & Embedded HW) Where we will head now Devices & Integrated Circuits (Semiconductors & Fabrication) Processor / Memory / I/O Functional Units (Registers, Adders, Muxes) Logic Gates Transistors Voltage / Currents

3 6.3 Motivation Now that you have some understanding Of how hardware is designed and works Of how software can be used to control hardware We will look at how to improve efficiency of computer systems and software so that we can start to understand why HW companies create the structures they do (multicore processors) we can begin to intelligently take advantage of the capabilities the HW gives us we can start to understand why SW companies deal with some of the issues they do (efficiencies, etc.)

4 6.4 Computer Organization Three primary sets of components Processor Memory I/O (everything else) Tell us where things live? Running code Compiled program (not running) Circuitry to execute code Source code file Data variables Data for the pixels being displayed on your screen

5 6.5 Input / Output Processor performs reads and writes to communicate with I/O devices just as it does with memory I/O devices have locations (i.e. registers) that contain data that the processor can access These registers are assigned unique addresses just like memory Processor Memory 3FF Video Interface 8 A D C FE may signify a white dot at a particular location This could just as easily be the command and data register from the LCD shield Or the PORT/DDR registers. 8 FE FE WRITE a = 6 hex in ASCII Keyboard Interface 4 6

6 6.6 Processor 3 Primary Components inside a processor ALU Registers Control Circuitry Connects to memory and I/O via address, data, and control buses (bus = group of wires) Processor Bus Addr Memory 2 Data 3 4 Control 5 6

7 6.7 Arithmetic and Logic Unit (ALU) Executes arithmetic operations like addition and subtraction along with logical operations (AND, OR, etc.) Processor Memory out op. ALU ADD, SUB, AND, OR in in2 Addr Data Control

8 6.8 Registers Some are for general use by software Registers provide fast, temporary storage locations within the processor (to avoid having to read/write slow memory) Others are required for specific purposes to ensure proper operation of the hardware Processor out op. ALU ADD, SUB, AND, OR in in2 R-R5 PC Addr Data Control Memory

9 6.9 General Purpose Registers Registers available to software instructions for use by the programmer/compiler Instructions use these registers as inputs (source locations) and outputs (destination locations) Processor out op. ALU ADD, SUB, AND, OR in in2 R-R5 PC Addr Data Control Memory

10 6. What if we didn t have registers? Example w/o registers: F = (X+Y) (X*Y) Requires an ADD instruction, MULtiply instruction, and SUBtract Instruction w/o registers ADD: Load X and Y from memory, store result to memory MUL: Load X and Y again from mem., store result to memory SUB: Load results from ADD and MUL and store result to memory 9 memory accesses Processor out op. ALU ADD, SUB, AND, OR in in2 R-R5 PC Addr Data Control Memory X Y F

11 6. What if we have registers? Example w/ registers: F = (X+Y) (X*Y) Load X and Y into registers ADD: R + R and store result in R2 MUL: R * R and store result in R3 SUB: R2 R3 and store result in R4 Store R4 back to memory 3 total memory access Processor out op. ALU ADD, SUB, AND, OR in in2 PC X Y R-R5 Addr Data Control Memory X Y F

12 6.2 Other Registers Some bookkeeping information is needed to make the processor operate correctly Example: Program Counter (PC) Recall that the processor must fetch instructions from memory before decoding and executing them PC register holds the address of the next instruction to fetch Processor out op. ALU ADD, SUB, AND, OR in in2 R-R5 PC Addr Data Control Memory

13 6.3 Fetching an Instruction To fetch an instruction PC contains the address of the instruction The value in the PC is placed on the address bus and the memory is told to read The PC is incremented, and the process is repeated for the next instruction Processor out op. ALU ADD, SUB, AND, OR in in2 R-R5 PC PC = Addr = Addr Data = inst. machine code Data Control = Read Control Memory FF inst. inst. 2 inst. 3 inst. 4 inst. 5

14 6.4 Fetching an Instruction To fetch an instruction PC contains the address of the instruction The value in the PC is placed on the address bus and the memory is told to read The PC is incremented, and the process is repeated for the next instruction Processor out op. ALU ADD, SUB, AND, OR in in2 R-R5 PC PC = Addr = Addr Data = inst.2 machine code Data Control = Read Control Memory FF inst. inst. 2 inst. 3 inst. 4 inst. 5

15 6.5 Control Circuitry Control circuitry is used to decode the instruction and then generate the necessary signals to complete its execution Controls the ALU Selects registers to be used as source and destination locations (using muxes) Processor out op. ALU ADD, SUB, AND, OR Control in in2 R-R5 PC Addr Data Control Memory FF inst. inst. 2 inst. 3 inst. 4 inst. 5

16 6.6 Control Circuitry Assume x2 is machine code for an ADD instruction of R2 = R + R Control Logic will select the registers (R and R) tell the ALU to add select the destination register (R2) Processor ADD Control PC Addr Memory 2 inst. 2 out ALU ADD in in2 R-R5 2 Data Control FF inst. 3 inst. 4 inst. 5

17 6.7 DESIGN OF A SIMPLE INSTRUCTIONS SET AND PROCESSOR

18 6.8 What Shall We Do? Let's design a simple processor to understand the entire flow from writing software to designing the hardware This may not be the most advanced processor but the goal is to give you a fully working example from software to hardware

19 6.9 Instruction Sets Defines the software interface of the processor and memory system Instruction set is the vocabulary the HW processor can understand and the SW is composed with Usually the compiler is the one that translates the software Most assembly/machine instructions fall into one of three categories Arithmetic/Logic Data Transfer (to and from memory) Control (branch, subroutine call, etc.)

20 6.2 Instruction Set Architecture (ISA) 2 approaches CISC = Complex instruction set computer Large, rich vocabulary More work per instruction, slower clock cycle RISC = Reduced instruction set computer Small, basic, but sufficient vocabulary Less work per instruction, faster clock cycle Usually a simple and small set of instructions with regular format facilitates building faster processors

21 6.2 The Instruction Set () To start we will define the instruction set Let's make this a simple calculator-like processor that can perform at least the following 3 operations: ADD SUB AND Goal is to evaluate simple arithmetic expressions: (7+4-5)&3 Let's use 4-bit data values (i.e. all data operands will be 4-bits) To keep the number of bits needed to code an instruction to a minimum, let's use an ACCumulator-based architecture where the ACC register is always one implied operand ADD 7 means: ACC += 7 SUB 5 means: ACC -= 5

22 6.22 The Instruction Set (2) Let's assume the output of this computer is just 4 LED's to display a 4-bit binary number We'll provide some additional instructions to help us perform the calculations: Load constant (Acc = const) Clear (Acc = ) Out (OUT = Acc) That leaves us with 6 total instructions How many bits do we need for the opcode of our instructions? 3-bits If we want to store data/constants in our instructions (e.g. ADD 7, SUB 5) how many additional bits do we need in our instruction? 4-bits Instructions need 3 opcode + 4 data bits = 7-bits Let's round up to 8-bits for each instruction Output LEDs (Display = 7 = 2 ) Opcode (3-bits) Computer System Unu sed Constant (4-bits) Chosen Instruction Format

23 6.23 Compilation Consider the following "high-level" code ( ) & 3 "Compile" it to an appropriate instruction sequence (i.e assembly) Assembly refers to the human readable syntax of each instruction CLR ADD 7 SUB 4 ADD 6 AND 3 Now we need to convert to binary Instruction Set Summary ADD k (ACC += k) SUB k (ACC -= k) AND k (ACC &= k) LOAD k (ACC = k) CLR (ACC = ) OUT (OUT = ACC)

24 6.24 Defining the Machine Code Machine code refers to the binary representation of each instruction. We first need to define the actual opcodes so we can translate the assembly you wrote on the previous slide into binary for the hardware to execute Before we do that, let's consider the hardware design as this will help us choose appropriate opcodes

25 EE9 ALU 6.25 Arithmetic and Logic Units Let's use the ALU we designed in a previous unit We will design what is inside this block. X X X2 X3 Y Y F2 F F R R R2 R3 We just made up these code assignments and the various operations. Remember, we definitely need to support ADD, SUB, AND, and CLR (R=). F[2:] Op./Result R = X + Y R = X - Y R = X R = Y - X R = X & Y Unused Y2 Y3 R = Unused

26 4-bit Binary Adder 6.26 Completed ALU X X X2 X3 Y Y Y2 Y3 I Y I S 2-to-, 4-bit wide mux I Y I S S = F F 2-to-, 4-bit wide mux 2-to-, 4-bit wide mux I Y I S A A A2 A3 B B B2 B3 Ci=F C C4 S S S2 S3 F[2:] Op. F[2:] Op. R = X + Y R = X & Y R = X - Y Unused R = X R = EE9 ALU R = Y - X Unused 2-to-, 4-bit wide mux I Y I S S3 = F2 R R R2 R3 S = F F' S2 = F' F X X F F F2 X2 X3 EE9 ALU

27 6.27 S = F F S = F F' S2 = F' F Ci = F S3 = F2 Control Logic R FS[2:] S S S2 Ci S3 X+Y X-Y X Y-X X & Y d unused d d d d d d d unused d d d d d F F2F S d d d F F2F S d d F F2F S2 F F2F F F2F Ci d d S3 d d d d d d

28 6.28 Defining the Machine Code Format Using the ALU design can you suggest opcodes for the various instructions? The accumulator (ACC) will be connected to the result of the ALU But should the ACC be connected to the X or Y input of the ALU? Important: We achieve Load by passing X through the ALU to the ACC, so we need the constant to come in on X (so ACC cannot) Instruction Set Summary ADD k (ACC += k) SUB k (ACC -= k) AND k (ACC &= k) LOAD k (ACC = k) CLR (ACC = ) OUT (OUT = ACC) F[2:] Op./Result R = X + Y R = X - Y R = X + = R = Y - X R = X & Y Unused R = Unused Instruc. OPCODE Op./Result ADD ACC = ACC + C OUT OUT = ACC LOAD ACC = C SUB ACC = ACC - C AND ACC = ACC & C - Unused CLR ACC = - Unused

29 6.29 Assembler Now translate the assembly you found from a few slides back to machine code and show it as 2 hex digits per instruction The "high-level" code was ( ) & 3 "Compile" it to an appropriate instruction sequence (i.e assembly) CLR = xc ADD 7 = x7 SUB 4 = x64 ADD 6 = x6 AND 3 = x83 Instruc. OPCODE Op./Result ADD ACC = ACC + C OUT OUT = ACC LOAD ACC = C SUB ACC = ACC - C AND ACC = ACC & C - Unused CLR ACC = - Unused Opcode (3-bits) Unu sed Constant (4-bits) Chosen Instruction Format

30 EE9 ALU 6.3 Processor Datapath Now let's consider the processor data path Instruction Fetch Logic Control 5-bit Counter Q A Q A A2 A3 RESET Q4 A4 CLR 32x8 Memory D D D4 D5 D6 D7 I I I2 I3 I4 or OUT_LD ACC_LD ACC_LD F2 F F X X X2 X3 Y Y Y2 Y3 R R R2 R3 ACC_LD D D Q Q ACC[3:] OUT_LD D D Q Q OUT[3:] LEDs

31 6.3 Sample Execution of SUB Instruction Fetch Logic 5-bit Counter CLR Q Q D D D4 D5 D6 D7 A A A2 A3 32x8 Memory I I I2 I3 I4 RESET Q4 A4 Control LEDs X X X2 X3 Y Y Y2 Y3 EE9 ALU R R R2 R3 F2 F F ACC_LD D D Q Q ACC[3:] OUT_LD D D Q Q OUT[3:] OUT_LD D D Q Q OUT[3:] OUT_LD ACC_LD ACC_LD or

32 6.32 A Problem Write assembly for: ((7 & 3) + (6 & 5)) LOAD 7 AND 3 No place to store result so we can compute (6&5) separately No place to store "temporary" results

33 6.33 A Solution Let's modify our processor as follows: Add two registers for temporary storage: R and R Could add more but we'll keep it simple A new instruction to save the ACC to a register: SAVE Rx (Rx = ACC) Update ALU instructions to be able to specify a register operand rather than just a constant ADD Rx (ACC = ACC + Rx) SUB Rx (ACC = ACC - Rx) AND RX (ACC = ACC & Rx) LOAD Rx (ACC = Rx) Update the instruction format to use the leftover bit to indicate whether the operand is a constant or should come from a register Opcode (3-bits) Opcode (3-bits) C/R C/R Constant (4-bits) Unused (3-bits) New Instruction Format Reg /

34 6.34 Updated Assembly Write assembly for: ( (7 & 3) + (6 & 5) ) New assembly & machine code LOAD 7 = x47 AND 3 = x83 SAVE R = xf LOAD 6 = x46 AND 5 = x85 ADD R = x OUT = x2 Instruc. OPCODE Op./Result ADD ACC = ACC + C/R OUT OUT = ACC LOAD ACC = X SUB ACC = ACC - C/R AND ACC = ACC & C/R - Unused CLR ACC = SAVE Rx Rx = ACC Opcode (3-bits) Opcode (3-bits) C/R C/R Constant (4-bits) Unused (3-bits) Reg / New Instruction Format

35 EE9 ALU 6.35 Updated Processor Datapath Instruction Fetch Logic Control 5-bit Counter Q A Q A A2 A3 RESET CLR Q4 A4 32x8 Memory D D D4 D5 D6 D7 I I I2 I3 I4 OUT_LD ACC_LD R_LD R_LD ACC[3:] 2-to-, 4-bit wide mux Data Registers R[3:] D[3:] Q[3:] I Y R I D[3:] Q[3:] S R R[3:] F2 F F X X X2 X3 Y Y Y2 Y3 R R R2 R3 D D ACC_LD Q Q ACC[3:] OUT_LD D D Q Q OUT[3:] LEDs

36 6.36 More Practice Write assembly for: ( (4&4) + (5&3) - (6&) + (8&3)) Try to use as few instructions as you can LOAD 6 AND SAVE R LOAD 4 AND 4 SAVE R LOAD 5 AND 3 ADD R SAVE R LOAD 8 AND 3 ADD R SUB R OUT Since we can only do ACC C/R, it means we should already have the sum of the other terms in ACC and then subtract. To compute 6& later would then require us to swap in the sum of the other terms into the ACC and then subtract, costing an extra instruction. Since we have many terms we can use R to keep "accumulating" the sum of more terms while we use the ACC to compute the current term. Opcode (3-bits) Opcode (3-bits) C/R C/R Constant (4-bits) Unused (3-bits) New Instruction Format Reg /

37 6.37 D[3:] Q[3:] D[3:] Q[3:] Data Registers ACC[3:] R_LD R_LD Instruction Fetch Logic 5-bit Counter CLR Q Q D D D4 D5 D6 D7 A A A2 A3 32x8 Memory I I I2 I3 I4 RESET Q4 A4 S I Y I 2-to-, 4-bit wide mux S I Y I 2-to-, 4-bit wide mux Control R R I I4 LEDs R[3:] R[3:] R_LD I R_LD X X X2 X3 Y Y Y2 Y3 EE9 ALU R R R2 R3 F2 F F ACC_LD D D Q Q ACC[3:] OUT_LD D D Q Q OUT[3:] OUT_LD D D Q Q OUT[3:] I OUT_LD ACC_LD ADD 7

38 6.38 D[3:] Q[3:] D[3:] Q[3:] Data Registers ACC[3:] R_LD R_LD Instruction Fetch Logic 5-bit Counter CLR Q Q D D D4 D5 D6 D7 A A A2 A3 32x8 Memory I I I2 I3 I4 RESET Q4 A4 S I Y I 2-to-, 4-bit wide mux S I Y I 2-to-, 4-bit wide mux Control R R I I4 LEDs R[3:] R[3:] R_LD I R_LD X X X2 X3 Y Y Y2 Y3 EE9 ALU R R R2 R3 F2 F F ACC_LD D D Q Q ACC[3:] OUT_LD D D Q Q OUT[3:] OUT_LD D D Q Q OUT[3:] I OUT_LD ACC_LD ADD R

39 6.39 D[3:] Q[3:] D[3:] Q[3:] Data Registers ACC[3:] R_LD R_LD Instruction Fetch Logic 5-bit Counter CLR Q Q D D D4 D5 D6 D7 A A A2 A3 32x8 Memory I I I2 I3 I4 RESET Q4 A4 S I Y I 2-to-, 4-bit wide mux S I Y I 2-to-, 4-bit wide mux Control R R I I4 LEDs R[3:] R[3:] R_LD I R_LD X X X2 X3 Y Y Y2 Y3 EE9 ALU R R R2 R3 F2 F F ACC_LD D D Q Q ACC[3:] OUT_LD D D Q Q OUT[3:] OUT_LD D D Q Q OUT[3:] I OUT_LD ACC_LD SAVE R x x x x x x x x x