Week 6: Processor Components

Size: px
Start display at page:

Download "Week 6: Processor Components"

Transcription

1 Week 6: Processor Components

2 Microprocessors So far, we ve been about making devices, such such as adders, counters and registers. The ultimate goal is to make a microprocessor, which is a digital device that processes input, can store values and produces output, according to a set of onboard instructions.

3 Microprocessors These devices are a combination of the units that we ve discussed so far: ú Registers to store values. ú Adders and shifters to process data. ú Finite state machines to control the process. Microprocessors are the basis of all computing since the 1970 s, and can be found in nearly every sort of electronics.

4 To get to this Assembly Language Processors Arithmetic Logic Units Devices Finite State Machines Flip-flops Circuits Logic Gates Transistors We built these

5 The Final Destination PCWriteCond PCWrite IorD MemRead MemWrite MemtoReg IRWrite Control Unit Opcode PCSource ALUOp ALUSrcB ALUSrcA RegWrite RegDst Shift left PC 0 1 Address Write data Memory Memory data Instruction [31-26] Instruction [25-21] Instruction [20-16] Instruction [15-0] Instruction Register Memory data register Registers Read reg 1 Read Read reg 2 data 1 Write reg Write data Sign extend Read data 2 A B Shift left A B Zero ALU result ALU ALU Out

6 Deconstructing processors Processors aren t so bad when you consider them piece by piece: Controller Thing Storage Thing Arithmetic Thing

7 The Arithmetic Thing aka: the Arithmetic Logic Unit (ALU)

8 Arithmetic Logic Unit The first microprocessor applications were calculators. ú Recall the unit on adders and subtractors. ú These are part of a larger structure called the arithmetic logic unit (ALU). This larger structure is responsible for the processing of all data values in a basic CPU.

9 ALU inputs The ALU performs all of the arithmetic operations covered in this course so far, and logical operations as well (AND, OR, NOT, etc.) C in,s ú The select bits indicate which operation is being performed (S2 is a mode select bit, indicating whether the ALU is in arithmetic or logic mode). ú The carry bit C in is used in operations such as incrementing an input value or the overall result. A G B VCNZ

10 ALU outputs In addition to the input signals, there are output signals V, C, N & Z which indicate special conditions in the arithmetic result: ú V: overflow condition C in,s The result of the operation could not be stored in the n bits of G, meaning that the result is incorrect. ú C: carry-out bit ú N: Negative indicator ú Z: Zero-condition indicator A G B VCNZ

11 The A of ALU To understand how the ALU does all of these operations, let s start with the arithmetic side. Fundamentally, this side is made of an adder / subtractor unit, which we ve seen already: Y 3 Y 2 Y 1 Y 0 Sub X 3 X 2 X 1 X 0 C out FA C 3 FA C 2 FA C 1 FA C in S 3 S 2 S 1 S 0

12 ALU block diagram In addition to data inputs and outputs, this circuit also has: ú outputs indicating the different conditions, ú inputs specifying the operation to perform (similar to Sub). Data input A Data input B Carry input Operation & Mode select A 0 A 1 A n-1 B 0 B 1 B n-1 C in S 0 S 1 S 2 n-bit ALU G 0 G 1 G n-1... C out V N Z Data output G Carry output Overflow indicator Negative indicator Zero indicator

13 Arithmetic components C in A B S 0 n n B input logic n X Y n-bit parallel adder G n G = X + Y + C in S 1 C out In addition to addition and subtraction, many more operations can be performed by manipulating what is added to input A, as shown in the diagram above.

14 Arithmetic operations If the input logic circuit on the left sends B straight through to the adder, result is G = A+B What if B was replaced by all ones instead? ú Result of addition operation: G = A-1 What if B was replaced by B? ú Result of addition operation: G = A-B-1 And what if B was replaced by all zeroes? ú Result is: G = A. (Not interesting, but useful!) à Instead of a Sub signal, the operation you want is signaled using the select bits S 0 & S 1.

15 Operation selection Select bits S 1 S 0 Y input Result Operation 0 0 All 0s G = A Transfer 0 1 B G = A+B Addition 1 0 B G = A+B Subtraction All 1s G = A-1 Decrement This is a good start! But something is missing Wait, what about the carry bit?

16 Full operation selection Select Input Operation S 1 S 0 Y C in =0 C in =1 0 0 All 0s G = A (transfer) G = A+1 (increment) 0 1 B G = A+B (add) G = A+B B G = A+B G = A+B+1 (subtract) 1 1 All 1s G = A-1 (decrement) G = A (transfer) Based on the values on the select bits and the carry bit, we can perform any number of basic arithmetic operations by manipulating what value is added to A.

17 The L of ALU We also want a circuit that can perform logical operations, in addition to arithmetic ones. How do we tell which operation to perform? ú Another select bit! A B 4-to-1 mux If S 2 = 1, then logic circuit block is activated. Multiplexer is used to determine which block (logical or arithmetic) goes to the output. S 0 S G

18 ALU block diagram In addition to data inputs and outputs, this circuit also has: ú outputs indicating the different conditions, ú inputs specifying the operation to perform (similar to Sub). Data input A Data input B Carry input Operation & Mode select A 0 A 1 A n-1 B 0 B 1 B n-1 C in S 0 S 1 S 2 n-bit ALU G 0 G 1 G n-1... C out V N Z Data output G Carry output Overflow indicator Negative indicator Zero indicator

19 Single ALU Stage C i A i B i C C i+1 i V A i N Z B i Arithmetic circuit G i S 0 S 1 S 0 S 1 0 G i 1 A i B i S 0 S 1 Logic circuit G i S 2

20 What about multiplication? Multiplication (and division) operations are always more complicated than other arithmetic (plus, minus) or logical (AND, OR) operations. Three major ways that multiplication can be implemented in circuitry: ú Layered rows of adder units. ú An adder/shifter circuit ú Booth s Algorithm

21 Break

22 Multiplication Multiplier circuits can be constructed as an array of adder circuits. This can get a little expensive as the size of the operands grows. Is there an alternative to this circuit?

23 Multiplication Revisiting grade 3 math 123 x x x x x

24 Multiplication And now, in binary 101 x x x x x

25 Booth s Algorithm Devised as a way to take advantage of circuits where shifting is cheaper than adding, or where space is at a premium. ú Based on the premise that when multiplying by certain values (e.g. 99), it can be easier to think of this operation as a difference between two products. Consider the shortcut method when multiplying a given decimal value X by 9999: ú X*9999 = X*10000 X*1 Now consider the equivalent problem in binary: ú X* = X* X*1

26 Booth s Algorithm This idea is triggered on cases where two neighboring digits in an operand are different. ú If digits at i and i-1 are 0 and 1, the multiplicand is added to the result at position i. ú If digits at i and i-1 are 1 and 0, the multiplicand is subtracted from the result at position i. The result is always a value whose size is the sum of the sizes of the two multiplicands.

27 Booth s Algorithm Example: x B A Add B here Subtract B from here Sign extend this before adding

28 Booth s Algorithm We need to make this work in hardware. ú Option #1: Have hardware set up to compare neighbouring bits at every position in A, with adders in place for when the bits don t match. Problem: This is a lot of hardware, which Booth s Algorithm is trying to avoid. ú Option #2: Have hardware set up to compare tw0 neighbouring bits, and have them move down through A, looking for mismatched pairs. Problem: Hardware doesn t move like that. Oops.

29 Booth s Algorithm Still need to make this work in hardware ú Option #3: Have hardware set up to compare tw0 neighbouring bits in the lowest position of A, and looking for mismatched pairs in A by shifting A to the right one bit at a time. Solution! This could work, but the accumulated solution P would have to shift one bit at a time as well, so that when B is added or subtracted, it s from the correct position.

30 Booth s Algorithm Note: unlike the accumulator, the bits here are being shifted to the right! Steps in Booth s Algorithm: 1. Designate the two multiplicands as A & B, and the result as some product P. 2. Add an extra zero bit to the right-most side of A. 3. Repeat the following for each original bit in A: a) If the last two bits of A are the same, do nothing. b) If the last two bits of A are 01, then add B to the highest bits of P. c) If the last two bits of A are 10, then subtract B from the highest bits of P. d) Perform one-digit arithmetic right-shift on both P and A. 4. The result in P is the product of A and B.

31 Booth s Algorithm Example Example: (-5) * 2 Steps #1 & #2: ú A = -5 à Add extra zero to the right à A = ú B = 2 à ú -B = -2 à ú P = 0 à

32 Booth s Algorithm Example Step #3 (repeat 5 times): ú Check last two digits of A: ú Since digits are 10, subtract B from the most significant digits of P: P B P ú Arithmetic shift P and A one bit to the right: A = P =

33 Booth s Algorithm Example Step #3 (repeat 4 more times): ú Check last two digits of A: ú Since digits are 11, do nothing to P. ú Arithmetic shift P and A one bit to the right: A = P =

34 Booth s Algorithm Example Step #3 (repeat 3 more times): ú Check last two digits of A: ú Since digits are 01, add B to the most significant digits of P: P B P ú Arithmetic shift P and A one bit to the right: A = P =

35 Booth s Algorithm Example Step #3 (repeat 2 more times): ú Check last two digits of A: ú Since digits are 10, subtract B from the most significant digits of P: P B P ú Arithmetic shift P and A one bit to the right: A = P =

36 Booth s Algorithm Example Step #3 (final time): ú Check last two digits of A: ú Since digits are 11, do nothing to P: ú Arithmetic shift P and A one bit to the right: A = P = Final product: P = = -10

37 Reflections on multiplication A popular version of this algorithm involves copying A into the lower bits of P, so that the testing and shifting only takes place in P. ú Also good for maintaining the original value of A. Multiplication isn t as common an operation as addition or subtraction, but occurs enough that its implementation is handled in the hardware, rather than by the CPU. Most common multiplication and division operations are powers of 2. For this, the shift register is used instead of the multiplier circuit.

38 Shifter unit D3 D2 D1 D0 S0 S S1 S S1 S S1 S S1 S0 4-to-1 MUX 4-to-1 MUX 4-to-1 MUX 4-to-1 MUX Barrel shifter acts alongside ALU to shift data elements according to S 0 and S 1. ú ú Y3 S1S0 = 00 : Y3Y2Y1Y0 = D3 D2 D1 D0 S1S0 = 01 : Y3 Y2 Y1 Y0 = D2 D1 D0 D3 Y2 Y1 Y0

39 Function Unit A B Constant in 1 0 MuxB select n Address out Data out G select A B B V,C,N,Z S 2:0,C in ALU G H select I R Shifter H I L n n 1 0 MuxF select F So where do A and B come from?

40 The Storage Thing aka: the register file and main memory More on this next time

Announcements. This week: no lab, no quiz, just midterm

Announcements. This week: no lab, no quiz, just midterm CSC258 Week 7 Announcements This week: no lab, no quiz, just midterm 2 Recap ALU Multiplication 3 To implement multiplication, we basically repeatedly do three things AND (one-bit multiplication) Addition

More information

CPE 335. Basic MIPS Architecture Part II

CPE 335. Basic MIPS Architecture Part II CPE 335 Computer Organization Basic MIPS Architecture Part II Dr. Iyad Jafar Adapted from Dr. Gheith Abandah slides http://www.abandah.com/gheith/courses/cpe335_s08/index.html CPE232 Basic MIPS Architecture

More information

LECTURE 6. Multi-Cycle Datapath and Control

LECTURE 6. Multi-Cycle Datapath and Control LECTURE 6 Multi-Cycle Datapath and Control SINGLE-CYCLE IMPLEMENTATION As we ve seen, single-cycle implementation, although easy to implement, could potentially be very inefficient. In single-cycle, we

More information

Topic #6. Processor Design

Topic #6. Processor Design Topic #6 Processor Design Major Goals! To present the single-cycle implementation and to develop the student's understanding of combinational and clocked sequential circuits and the relationship between

More information

Lecture 5 and 6. ICS 152 Computer Systems Architecture. Prof. Juan Luis Aragón

Lecture 5 and 6. ICS 152 Computer Systems Architecture. Prof. Juan Luis Aragón ICS 152 Computer Systems Architecture Prof. Juan Luis Aragón Lecture 5 and 6 Multicycle Implementation Introduction to Microprogramming Readings: Sections 5.4 and 5.5 1 Review of Last Lecture We have seen

More information

Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: Data Paths and Microprogramming

Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: Data Paths and Microprogramming Computer Science 324 Computer Architecture Mount Holyoke College Fall 2007 Topic Notes: Data Paths and Microprogramming We have spent time looking at the MIPS instruction set architecture and building

More information

ECE369. Chapter 5 ECE369

ECE369. Chapter 5 ECE369 Chapter 5 1 State Elements Unclocked vs. Clocked Clocks used in synchronous logic Clocks are needed in sequential logic to decide when an element that contains state should be updated. State element 1

More information

Processor: Multi- Cycle Datapath & Control

Processor: Multi- Cycle Datapath & Control Processor: Multi- Cycle Datapath & Control (Based on text: David A. Patterson & John L. Hennessy, Computer Organization and Design: The Hardware/Software Interface, 3 rd Ed., Morgan Kaufmann, 27) COURSE

More information

RISC Processor Design

RISC Processor Design RISC Processor Design Single Cycle Implementation - MIPS Virendra Singh Indian Institute of Science Bangalore virendra@computer.org Lecture 13 SE-273: Processor Design Feb 07, 2011 SE-273@SERC 1 Courtesy:

More information

CSE 2021 COMPUTER ORGANIZATION

CSE 2021 COMPUTER ORGANIZATION CSE 2021 COMPUTER ORGANIZATION HUGH LAS CHESSER 1012U HUGH CHESSER CSEB 1012U W10-M Agenda Topics: 1. Multiple cycle implementation review 2. State Machine 3. Control Unit implementation for Multi-cycle

More information

ﻪﺘﻓﺮﺸﻴﭘ ﺮﺗﻮﻴﭙﻣﺎﻛ يرﺎﻤﻌﻣ MIPS يرﺎﻤﻌﻣ data path and ontrol control

ﻪﺘﻓﺮﺸﻴﭘ ﺮﺗﻮﻴﭙﻣﺎﻛ يرﺎﻤﻌﻣ MIPS يرﺎﻤﻌﻣ data path and ontrol control معماري كامپيوتر پيشرفته معماري MIPS data path and control abbasi@basu.ac.ir Topics Building a datapath support a subset of the MIPS-I instruction-set A single cycle processor datapath all instruction actions

More information

REGISTER TRANSFER LANGUAGE

REGISTER TRANSFER LANGUAGE REGISTER TRANSFER LANGUAGE The operations executed on the data stored in the registers are called micro operations. Classifications of micro operations Register transfer micro operations Arithmetic micro

More information

CC 311- Computer Architecture. The Processor - Control

CC 311- Computer Architecture. The Processor - Control CC 311- Computer Architecture The Processor - Control Control Unit Functions: Instruction code Control Unit Control Signals Select operations to be performed (ALU, read/write, etc.) Control data flow (multiplexor

More information

Chapter 5: The Processor: Datapath and Control

Chapter 5: The Processor: Datapath and Control Chapter 5: The Processor: Datapath and Control Overview Logic Design Conventions Building a Datapath and Control Unit Different Implementations of MIPS instruction set A simple implementation of a processor

More information

Multicycle conclusion

Multicycle conclusion Multicycle conclusion The last few lectures covered a lot of material! We introduced a multicycle datapath, where different instructions take different numbers of cycles to execute. A multicycle unit is

More information

Mapping Control to Hardware

Mapping Control to Hardware C A P P E N D I X A custom format such as this is slave to the architecture of the hardware and the instruction set it serves. The format must strike a proper compromise between ROM size, ROM-output decoding,

More information

Points available Your marks Total 100

Points available Your marks Total 100 CSSE 3 Computer Architecture I Rose-Hulman Institute of Technology Computer Science and Software Engineering Department Exam Name: Section: 3 This exam is closed book. You are allowed to use the reference

More information

RISC Design: Multi-Cycle Implementation

RISC Design: Multi-Cycle Implementation RISC Design: Multi-Cycle Implementation Virendra Singh Associate Professor Computer Architecture and Dependable Systems Lab Department of Electrical Engineering Indian Institute of Technology Bombay http://www.ee.iitb.ac.in/~viren/

More information

Chapter 5 Solutions: For More Practice

Chapter 5 Solutions: For More Practice Chapter 5 Solutions: For More Practice 1 Chapter 5 Solutions: For More Practice 5.4 Fetching, reading registers, and writing the destination register takes a total of 300ps for both floating point add/subtract

More information

Inf2C - Computer Systems Lecture 12 Processor Design Multi-Cycle

Inf2C - Computer Systems Lecture 12 Processor Design Multi-Cycle Inf2C - Computer Systems Lecture 12 Processor Design Multi-Cycle Boris Grot School of Informatics University of Edinburgh Previous lecture: single-cycle processor Inf2C Computer Systems - 2017-2018. Boris

More information

CSE 2021 COMPUTER ORGANIZATION

CSE 2021 COMPUTER ORGANIZATION CSE 22 COMPUTER ORGANIZATION HUGH CHESSER CHESSER HUGH CSEB 2U 2U CSEB Agenda Topics:. Sample Exam/Quiz Q - Review 2. Multiple cycle implementation Patterson: Section 4.5 Reminder: Quiz #2 Next Wednesday

More information

Control Unit for Multiple Cycle Implementation

Control Unit for Multiple Cycle Implementation Control Unit for Multiple Cycle Implementation Control is more complex than in single cycle since: Need to define control signals for each step Need to know which step we are on Two methods for designing

More information

Processor (I) - datapath & control. Hwansoo Han

Processor (I) - datapath & control. Hwansoo Han Processor (I) - datapath & control Hwansoo Han Introduction CPU performance factors Instruction count - Determined by ISA and compiler CPI and Cycle time - Determined by CPU hardware We will examine two

More information

ECE260: Fundamentals of Computer Engineering

ECE260: Fundamentals of Computer Engineering Datapath for a Simplified Processor James Moscola Dept. of Engineering & Computer Science York College of Pennsylvania Based on Computer Organization and Design, 5th Edition by Patterson & Hennessy Introduction

More information

RISC Architecture: Multi-Cycle Implementation

RISC Architecture: Multi-Cycle Implementation RISC Architecture: Multi-Cycle Implementation Virendra Singh Associate Professor Computer Architecture and Dependable Systems Lab Department of Electrical Engineering Indian Institute of Technology Bombay

More information

Systems Architecture I

Systems Architecture I Systems Architecture I Topics A Simple Implementation of MIPS * A Multicycle Implementation of MIPS ** *This lecture was derived from material in the text (sec. 5.1-5.3). **This lecture was derived from

More information

Computer Architecture and Organization: L04: Micro-operations

Computer Architecture and Organization: L04: Micro-operations Computer Architecture and Organization: L4: Micro-operations By: A. H. Abdul Hafez Abdul.hafez@hku.edu.tr, ah.abdulhafez@gmail.com, hafez@research.iiit.ac.in 1 Outlines 1. Arithmetic microoperation 2.

More information

Major CPU Design Steps

Major CPU Design Steps Datapath Major CPU Design Steps. Analyze instruction set operations using independent RTN ISA => RTN => datapath requirements. This provides the the required datapath components and how they are connected

More information

Lets Build a Processor

Lets Build a Processor Lets Build a Processor Almost ready to move into chapter 5 and start building a processor First, let s review Boolean Logic and build the ALU we ll need (Material from Appendix B) operation a 32 ALU result

More information

RISC Architecture: Multi-Cycle Implementation

RISC Architecture: Multi-Cycle Implementation RISC Architecture: Multi-Cycle Implementation Virendra Singh Associate Professor Computer Architecture and Dependable Systems Lab Department of Electrical Engineering Indian Institute of Technology Bombay

More information

ENE 334 Microprocessors

ENE 334 Microprocessors ENE 334 Microprocessors Lecture 6: Datapath and Control : Dejwoot KHAWPARISUTH Adapted from Computer Organization and Design, 3 th & 4 th Edition, Patterson & Hennessy, 2005/2008, Elsevier (MK) http://webstaff.kmutt.ac.th/~dejwoot.kha/

More information

CSE 2021: Computer Organization Fall 2010 Solution to Assignment # 3: Multicycle Implementation

CSE 2021: Computer Organization Fall 2010 Solution to Assignment # 3: Multicycle Implementation CSE 2021: Computer Organization Fall 2010 Solution to Assignment # 3: Multicycle Implementation Note that these questions are taken from the previous final exmas of CSE2021 and should serve as practice

More information

The Processor: Datapath & Control

The Processor: Datapath & Control Chapter Five 1 The Processor: Datapath & Control We're ready to look at an implementation of the MIPS Simplified to contain only: memory-reference instructions: lw, sw arithmetic-logical instructions:

More information

Midterm. Sticker winners: if you got >= 50 / 67

Midterm. Sticker winners: if you got >= 50 / 67 CSC258 Week 8 Midterm Class average: 4.2 / 67 (6%) Highest mark: 64.5 / 67 Tests will be return in office hours. Make sure your midterm mark is correct on MarkUs Solution posted on the course website.

More information

CO Computer Architecture and Programming Languages CAPL. Lecture 18 & 19

CO Computer Architecture and Programming Languages CAPL. Lecture 18 & 19 CO2-3224 Computer Architecture and Programming Languages CAPL Lecture 8 & 9 Dr. Kinga Lipskoch Fall 27 Single Cycle Disadvantages & Advantages Uses the clock cycle inefficiently the clock cycle must be

More information

ECE 313 Computer Organization FINAL EXAM December 14, This exam is open book and open notes. You have 2 hours.

ECE 313 Computer Organization FINAL EXAM December 14, This exam is open book and open notes. You have 2 hours. This exam is open book and open notes. You have 2 hours. Problems 1-4 refer to a proposed MIPS instruction lwu (load word - update) which implements update addressing an addressing mode that is used in

More information

Boolean Unit (The obvious way)

Boolean Unit (The obvious way) oolean Unit (The obvious way) It is simple to build up a oolean unit using primitive gates and a mux to select the function. Since there is no interconnection between bits, this unit can be simply replicated

More information

ECE 341 Midterm Exam

ECE 341 Midterm Exam ECE 341 Midterm Exam Time allowed: 90 minutes Total Points: 75 Points Scored: Name: Problem No. 1 (10 points) For each of the following statements, indicate whether the statement is TRUE or FALSE: (a)

More information

COMPUTER ARCHITECTURE AND ORGANIZATION Register Transfer and Micro-operations 1. Introduction A digital system is an interconnection of digital

COMPUTER ARCHITECTURE AND ORGANIZATION Register Transfer and Micro-operations 1. Introduction A digital system is an interconnection of digital Register Transfer and Micro-operations 1. Introduction A digital system is an interconnection of digital hardware modules that accomplish a specific information-processing task. Digital systems vary in

More information

Alternative to single cycle. Drawbacks of single cycle implementation. Multiple cycle implementation. Instruction fetch

Alternative to single cycle. Drawbacks of single cycle implementation. Multiple cycle implementation. Instruction fetch Drawbacks of single cycle implementation Alternative to single cycle All instructions take the same time although some instructions are longer than others; e.g. load is longer than add since it has to

More information

Systems Architecture

Systems Architecture Systems Architecture Lecture 15: A Simple Implementation of MIPS Jeremy R. Johnson Anatole D. Ruslanov William M. Mongan Some or all figures from Computer Organization and Design: The Hardware/Software

More information

Multiple Cycle Data Path

Multiple Cycle Data Path Multiple Cycle Data Path CS 365 Lecture 7 Prof. Yih Huang CS365 1 Multicycle Approach Break up the instructions into steps, each step takes a cycle balance the amount of work to be done restrict each cycle

More information

ALUOut. Registers A. I + D Memory IR. combinatorial block. combinatorial block. combinatorial block MDR

ALUOut. Registers A. I + D Memory IR. combinatorial block. combinatorial block. combinatorial block MDR Microprogramming Exceptions and interrupts 9 CMPE Fall 26 A. Di Blas Fall 26 CMPE CPU Multicycle From single-cycle to Multicycle CPU with sequential control: Finite State Machine Textbook Edition: 5.4,

More information

UNIT-III REGISTER TRANSFER LANGUAGE AND DESIGN OF CONTROL UNIT

UNIT-III REGISTER TRANSFER LANGUAGE AND DESIGN OF CONTROL UNIT UNIT-III 1 KNREDDY UNIT-III REGISTER TRANSFER LANGUAGE AND DESIGN OF CONTROL UNIT Register Transfer: Register Transfer Language Register Transfer Bus and Memory Transfers Arithmetic Micro operations Logic

More information

Design of Digital Circuits 2017 Srdjan Capkun Onur Mutlu (Guest starring: Frank K. Gürkaynak and Aanjhan Ranganathan)

Design of Digital Circuits 2017 Srdjan Capkun Onur Mutlu (Guest starring: Frank K. Gürkaynak and Aanjhan Ranganathan) Microarchitecture Design of Digital Circuits 27 Srdjan Capkun Onur Mutlu (Guest starring: Frank K. Gürkaynak and Aanjhan Ranganathan) http://www.syssec.ethz.ch/education/digitaltechnik_7 Adapted from Digital

More information

Arithmetic Circuits. Design of Digital Circuits 2014 Srdjan Capkun Frank K. Gürkaynak.

Arithmetic Circuits. Design of Digital Circuits 2014 Srdjan Capkun Frank K. Gürkaynak. Arithmetic Circuits Design of Digital Circuits 2014 Srdjan Capkun Frank K. Gürkaynak http://www.syssec.ethz.ch/education/digitaltechnik_14 Adapted from Digital Design and Computer Architecture, David Money

More information

Contents. Chapter 9 Datapaths Page 1 of 28

Contents. Chapter 9 Datapaths Page 1 of 28 Chapter 9 Datapaths Page of 2 Contents Contents... 9 Datapaths... 2 9. General Datapath... 3 9.2 Using a General Datapath... 5 9.3 Timing Issues... 7 9.4 A More Complex General Datapath... 9 9.5 VHDL for

More information

Two-Level CLA for 4-bit Adder. Two-Level CLA for 4-bit Adder. Two-Level CLA for 16-bit Adder. A Closer Look at CLA Delay

Two-Level CLA for 4-bit Adder. Two-Level CLA for 4-bit Adder. Two-Level CLA for 16-bit Adder. A Closer Look at CLA Delay Two-Level CLA for 4-bit Adder Individual carry equations C 1 = g 0 +p 0, C 2 = g 1 +p 1 C 1,C 3 = g 2 +p 2 C 2, = g 3 +p 3 C 3 Fully expanded (infinite hardware) CLA equations C 1 = g 0 +p 0 C 2 = g 1

More information

THE HONG KONG UNIVERSITY OF SCIENCE & TECHNOLOGY Computer Organization (COMP 2611) Spring Semester, 2014 Final Examination

THE HONG KONG UNIVERSITY OF SCIENCE & TECHNOLOGY Computer Organization (COMP 2611) Spring Semester, 2014 Final Examination THE HONG KONG UNIVERSITY OF SCIENCE & TECHNOLOGY Computer Organization (COMP 2611) Spring Semester, 2014 Final Examination May 23, 2014 Name: Email: Student ID: Lab Section Number: Instructions: 1. This

More information

Microprogramming. Microprogramming

Microprogramming. Microprogramming Microprogramming Alternative way of specifying control FSM State -- bubble control signals in bubble next state given by signals on arc not a great language to specify when things are complex Treat as

More information

ECE 341 Midterm Exam

ECE 341 Midterm Exam ECE 341 Midterm Exam Time allowed: 75 minutes Total Points: 75 Points Scored: Name: Problem No. 1 (8 points) For each of the following statements, indicate whether the statement is TRUE or FALSE: (a) A

More information

Final Project: MIPS-like Microprocessor

Final Project: MIPS-like Microprocessor Final Project: MIPS-like Microprocessor Objective: The objective of this project is to design, simulate, and implement a simple 32-bit microprocessor with an instruction set that is similar to a MIPS.

More information

Binary Arithmetic Intro to Assembly Language CS 64: Computer Organization and Design Logic Lecture #3

Binary Arithmetic Intro to Assembly Language CS 64: Computer Organization and Design Logic Lecture #3 Binary Arithmetic Intro to Assembly Language CS 64: Computer Organization and Design Logic Lecture #3 Ziad Matni Dept. of Computer Science, UCSB Adding this Class The class is full I will not be adding

More information

Multicycle Approach. Designing MIPS Processor

Multicycle Approach. Designing MIPS Processor CSE 675.2: Introduction to Computer Architecture Multicycle Approach 8/8/25 Designing MIPS Processor (Multi-Cycle) Presentation H Slides by Gojko Babić and Elsevier Publishing We will be reusing functional

More information

Multi-cycle Approach. Single cycle CPU. Multi-cycle CPU. Requires state elements to hold intermediate values. one clock cycle or instruction

Multi-cycle Approach. Single cycle CPU. Multi-cycle CPU. Requires state elements to hold intermediate values. one clock cycle or instruction Multi-cycle Approach Single cycle CPU State element Combinational logic State element clock one clock cycle or instruction Multi-cycle CPU Requires state elements to hold intermediate values State Element

More information

Using a Hardware Description Language to Design and Simulate a Processor 5.8

Using a Hardware Description Language to Design and Simulate a Processor 5.8 5.8 Using a Hardware Description Language to Design and Simulate a Processor 5.8 As mentioned in Appix B, Verilog can describe processors for simulation or with the intention that the Verilog specification

More information

Chapter 4. The Processor. Computer Architecture and IC Design Lab

Chapter 4. The Processor. Computer Architecture and IC Design Lab Chapter 4 The Processor Introduction CPU performance factors CPI Clock Cycle Time Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS

More information

Arithmetic Logic Unit. Digital Computer Design

Arithmetic Logic Unit. Digital Computer Design Arithmetic Logic Unit Digital Computer Design Arithmetic Circuits Arithmetic circuits are the central building blocks of computers. Computers and digital logic perform many arithmetic functions: addition,

More information

Real Digital Problem Set #6

Real Digital Problem Set #6 Real igital Problem et #6. (2 points) ketch a block diagram for a magnitude comparator bit-slice circuit. Create K-maps to define the bit-slice circuit, and use them to find optimal logic equations. ketch

More information

Lecture 5: The Processor

Lecture 5: The Processor Lecture 5: The Processor CSCE 26 Computer Organization Instructor: Saraju P. ohanty, Ph. D. NOTE: The figures, text etc included in slides are borrowed from various books, websites, authors pages, and

More information

EECE 417 Computer Systems Architecture

EECE 417 Computer Systems Architecture EECE 417 Computer Systems Architecture Department of Electrical and Computer Engineering Howard University Charles Kim Spring 2007 1 Computer Organization and Design (3 rd Ed) -The Hardware/Software Interface

More information

Chapter 4 The Processor (Part 2)

Chapter 4 The Processor (Part 2) Department of Electr rical Eng ineering, Chapter 4 The Processor (Part 2) 王振傑 (Chen-Chieh Wang) ccwang@mail.ee.ncku.edu.tw ncku edu Feng-Chia Unive ersity Outline A Multicycle Implementation Mapping Control

More information

Tailoring the 32-Bit ALU to MIPS

Tailoring the 32-Bit ALU to MIPS Tailoring the 32-Bit ALU to MIPS MIPS ALU extensions Overflow detection: Carry into MSB XOR Carry out of MSB Branch instructions Shift instructions Slt instruction Immediate instructions ALU performance

More information

EE260: Logic Design, Spring n Integer multiplication. n Booth s algorithm. n Integer division. n Restoring, non-restoring

EE260: Logic Design, Spring n Integer multiplication. n Booth s algorithm. n Integer division. n Restoring, non-restoring EE 260: Introduction to Digital Design Arithmetic II Yao Zheng Department of Electrical Engineering University of Hawaiʻi at Mānoa Overview n Integer multiplication n Booth s algorithm n Integer division

More information

CSE 141 Computer Architecture Summer Session Lecture 3 ALU Part 2 Single Cycle CPU Part 1. Pramod V. Argade

CSE 141 Computer Architecture Summer Session Lecture 3 ALU Part 2 Single Cycle CPU Part 1. Pramod V. Argade CSE 141 Computer Architecture Summer Session 1 2004 Lecture 3 ALU Part 2 Single Cycle CPU Part 1 Pramod V. Argade Reading Assignment Announcements Chapter 5: The Processor: Datapath and Control, Sec. 5.3-5.4

More information

Problem 4 The order, from easiest to hardest, is Bit Equal, Split Register, Replace Under Mask.

Problem 4 The order, from easiest to hardest, is Bit Equal, Split Register, Replace Under Mask. HW3 Solutions (CS552 Spring 2013) Grade distribution: (Total: 100) - Verilog submission of problems 1), 2) and 3) carry 15 points each(total: 45 points) - Written part of problem 1), 2) and 3) carry 5

More information

Winter 2002 FINAL EXAMINATION

Winter 2002 FINAL EXAMINATION University of Calgary Department of Electrical and Computer Engineering ENCM 369: Computer Organization Instructors: Dr. S. A. Norman (L01) and Dr. S. Yanushkevich (L02) Note for Winter 2005 students Winter

More information

COMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 4. The Processor

COMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 4. The Processor COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition The Processor - Introduction

More information

Design Example: 4-bit Multiplier

Design Example: 4-bit Multiplier Design Example: 4-bit Multiplier Consider how we normally multiply numbers: 123 x 264 492 7380 24600 32472 Binary multiplication is similar. (Note that the product of two 4-bit numbers is potentially an

More information

Computer Architecture V Fall Practice Exam Questions

Computer Architecture V Fall Practice Exam Questions Computer Architecture V22.0436 Fall 2002 Practice Exam Questions These are practice exam questions for the material covered since the mid-term exam. Please note that the final exam is cumulative. See the

More information

Chapter 4. Instruction Execution. Introduction. CPU Overview. Multiplexers. Chapter 4 The Processor 1. The Processor.

Chapter 4. Instruction Execution. Introduction. CPU Overview. Multiplexers. Chapter 4 The Processor 1. The Processor. COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor The Processor - Introduction

More information

Single vs. Multi-cycle Implementation

Single vs. Multi-cycle Implementation Single vs. Multi-cycle Implementation Multicycle: Instructions take several faster cycles For this simple version, the multi-cycle implementation could be as much as 1.27 times faster (for a typical instruction

More information

The Processor (1) Jinkyu Jeong Computer Systems Laboratory Sungkyunkwan University

The Processor (1) Jinkyu Jeong Computer Systems Laboratory Sungkyunkwan University The Processor (1) Jinkyu Jeong (jinkyu@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong (jinkyu@skku.edu)

More information

COMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 4. The Processor

COMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 4. The Processor COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle

More information

CMOS VLSI Design. MIPS Processor Example. Outline

CMOS VLSI Design. MIPS Processor Example. Outline COS VLSI Design IPS Processor Example Outline Design Partitioning IPS Processor Example Architecture icroarchitecture Logic Design Circuit Design Physical Design Fabrication, Packaging, Testing Slide 2

More information

COMPUTER ARCHITECTURE AND ORGANIZATION. Operation Add Magnitudes Subtract Magnitudes (+A) + ( B) + (A B) (B A) + (A B)

COMPUTER ARCHITECTURE AND ORGANIZATION. Operation Add Magnitudes Subtract Magnitudes (+A) + ( B) + (A B) (B A) + (A B) Computer Arithmetic Data is manipulated by using the arithmetic instructions in digital computers. Data is manipulated to produce results necessary to give solution for the computation problems. The Addition,

More information

Binary Multiplication

Binary Multiplication inary Multiplication The key to multiplication was memorizing a digit-by-digit table Everything else was just adding 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 2 2 4 6 8 2 4 6 8 3 3 6 9 2 5 8 2 24 27 + You ve got

More information

Number Systems and Computer Arithmetic

Number Systems and Computer Arithmetic Number Systems and Computer Arithmetic Counting to four billion two fingers at a time What do all those bits mean now? bits (011011011100010...01) instruction R-format I-format... integer data number text

More information

EE457. Note: Parts of the solutions are extracted from the solutions manual accompanying the text book.

EE457. Note: Parts of the solutions are extracted from the solutions manual accompanying the text book. EE457 Instructor: G. Puvvada ======================================================================= Homework 5b, Solution ======================================================================= Note:

More information

Winter 2006 FINAL EXAMINATION Auxiliary Gymnasium Tuesday, April 18 7:00pm to 10:00pm

Winter 2006 FINAL EXAMINATION Auxiliary Gymnasium Tuesday, April 18 7:00pm to 10:00pm University of Calgary Department of Electrical and Computer Engineering ENCM 369: Computer Organization Lecture Instructor for L01 and L02: Dr. S. A. Norman Winter 2006 FINAL EXAMINATION Auxiliary Gymnasium

More information

CS 5803 Introduction to High Performance Computer Architecture: Arithmetic Logic Unit. A.R. Hurson 323 CS Building, Missouri S&T

CS 5803 Introduction to High Performance Computer Architecture: Arithmetic Logic Unit. A.R. Hurson 323 CS Building, Missouri S&T CS 5803 Introduction to High Performance Computer Architecture: Arithmetic Logic Unit A.R. Hurson 323 CS Building, Missouri S&T hurson@mst.edu 1 Outline Motivation Design of a simple ALU How to design

More information

CS 2506 Computer Organization II Test 1. Do not start the test until instructed to do so! printed

CS 2506 Computer Organization II Test 1. Do not start the test until instructed to do so! printed Instructions: Print your name in the space provided below. This examination is closed book and closed notes, aside from the permitted one-page formula sheet. No calculators or other computing devices may

More information

Cpr E 281 FINAL PROJECT ELECTRICAL AND COMPUTER ENGINEERING IOWA STATE UNIVERSITY. FINAL Project. Objectives. Project Selection

Cpr E 281 FINAL PROJECT ELECTRICAL AND COMPUTER ENGINEERING IOWA STATE UNIVERSITY. FINAL Project. Objectives. Project Selection Objectives The main objective of the final project is to teach you how to put together all of the class material that you have learned so far in order to program the Altera DE2 board to carry out an independent

More information

CSEN 601: Computer System Architecture Summer 2014

CSEN 601: Computer System Architecture Summer 2014 CSEN 601: Computer System Architecture Summer 2014 Practice Assignment 5 Solutions Exercise 5-1: (Midterm Spring 2013) a. What are the values of the control signals (except ALUOp) for each of the following

More information

The Need of Datapath or Register Transfer Logic. Number 1 Number 2 Number 3 Number 4. Numbers from 1 to million. Register

The Need of Datapath or Register Transfer Logic. Number 1 Number 2 Number 3 Number 4. Numbers from 1 to million. Register The Need of Datapath or Register Transfer Logic Number 1 Number 2 Number 3 Number 4 Numbers from 1 to million Register (a) (b) Circuits to add several numbers: (a) combinational circuit to add four numbers;

More information

Note- E~ S. \3 \S U\e. ~ ~s ~. 4. \\ o~ (fw' \i<.t. (~e., 3\0)

Note- E~ S. \3 \S U\e. ~ ~s ~. 4. \\ o~ (fw' \i<.t. (~e., 3\0) 5.4 A Multicycle Implementation 377 Similarly, if we had a machine with more powerful operations and addressing modes, instructions could vary from three or four functional unit delays to tens or even

More information

Arithmetic-logic units

Arithmetic-logic units Arithmetic-logic units An arithmetic-logic unit, or ALU, performs many different arithmetic and logic operations. The ALU is the heart of a processor you could say that everything else in the CPU is there

More information

DC57 COMPUTER ORGANIZATION JUNE 2013

DC57 COMPUTER ORGANIZATION JUNE 2013 Q2 (a) How do various factors like Hardware design, Instruction set, Compiler related to the performance of a computer? The most important measure of a computer is how quickly it can execute programs.

More information

CS/COE0447: Computer Organization

CS/COE0447: Computer Organization CS/COE0447: Computer Organization and Assembly Language Chapter 3 Sangyeun Cho Dept. of Computer Science Five classic components I am like a control tower I am like a pack of file folders I am like a conveyor

More information

CS/COE0447: Computer Organization

CS/COE0447: Computer Organization CS/COE0447: Computer Organization and Assembly Language Datapath and Control Sangyeun Cho Dept. of Computer Science A simple MIPS We will design a simple MIPS processor that supports a small instruction

More information

CS/COE0447: Computer Organization

CS/COE0447: Computer Organization A simple MIPS CS/COE447: Computer Organization and Assembly Language Datapath and Control Sangyeun Cho Dept. of Computer Science We will design a simple MIPS processor that supports a small instruction

More information

CS/COE0447: Computer Organization

CS/COE0447: Computer Organization Five classic components CS/COE0447: Computer Organization and Assembly Language I am like a control tower I am like a pack of file folders Chapter 3 I am like a conveyor belt + service stations I exchange

More information

Initial Representation Finite State Diagram. Logic Representation Logic Equations

Initial Representation Finite State Diagram. Logic Representation Logic Equations Control Implementation Alternatives Control may be designed using one of several initial representations. The choice of sequence control, and how logic is represented, can then be determined independently;

More information

COMPUTER ORGANIZATION AND DESIGN. The Hardware/Software Interface. Chapter 4. The Processor: A Based on P&H

COMPUTER ORGANIZATION AND DESIGN. The Hardware/Software Interface. Chapter 4. The Processor: A Based on P&H COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface Chapter 4 The Processor: A Based on P&H Introduction We will examine two MIPS implementations A simplified version A more realistic pipelined

More information

Register Transfer and Micro-operations

Register Transfer and Micro-operations Register Transfer Language Register Transfer Bus Memory Transfer Micro-operations Some Application of Logic Micro Operations Register Transfer and Micro-operations Learning Objectives After reading this

More information

Homework 3. Assigned on 02/15 Due time: midnight on 02/21 (1 WEEK only!) B.2 B.11 B.14 (hint: use multiplexors) CSCI 402: Computer Architectures

Homework 3. Assigned on 02/15 Due time: midnight on 02/21 (1 WEEK only!) B.2 B.11 B.14 (hint: use multiplexors) CSCI 402: Computer Architectures Homework 3 Assigned on 02/15 Due time: midnight on 02/21 (1 WEEK only!) B.2 B.11 B.14 (hint: use multiplexors) 1 CSCI 402: Computer Architectures Arithmetic for Computers (2) Fengguang Song Department

More information

ECE 3056: Architecture, Concurrency and Energy of Computation. Single and Multi-Cycle Datapaths: Practice Problems

ECE 3056: Architecture, Concurrency and Energy of Computation. Single and Multi-Cycle Datapaths: Practice Problems ECE 3056: Architecture, Concurrency and Energy of Computation Single and Multi-Cycle Datapaths: Practice Problems 1. Consider the single cycle SPIM datapath. a. Specify the values of the control signals

More information

CS232 Final Exam May 5, 2001

CS232 Final Exam May 5, 2001 CS232 Final Exam May 5, 2 Name: This exam has 4 pages, including this cover. There are six questions, worth a total of 5 points. You have 3 hours. Budget your time! Write clearly and show your work. State

More information

CS 31: Intro to Systems Digital Logic. Kevin Webb Swarthmore College February 2, 2016

CS 31: Intro to Systems Digital Logic. Kevin Webb Swarthmore College February 2, 2016 CS 31: Intro to Systems Digital Logic Kevin Webb Swarthmore College February 2, 2016 Reading Quiz Today Hardware basics Machine memory models Digital signals Logic gates Circuits: Borrow some paper if

More information

Kinds Of Data CHAPTER 3 DATA REPRESENTATION. Numbers Are Different! Positional Number Systems. Text. Numbers. Other

Kinds Of Data CHAPTER 3 DATA REPRESENTATION. Numbers Are Different! Positional Number Systems. Text. Numbers. Other Kinds Of Data CHAPTER 3 DATA REPRESENTATION Numbers Integers Unsigned Signed Reals Fixed-Point Floating-Point Binary-Coded Decimal Text ASCII Characters Strings Other Graphics Images Video Audio Numbers

More information