ALUOut. Registers A. I + D Memory IR. combinatorial block. combinatorial block. combinatorial block MDR

Transcription

1 Microprogramming Exceptions and interrupts 9 CMPE Fall 26 A. Di Blas Fall 26 CMPE CPU Multicycle From single-cycle to Multicycle CPU with sequential control: Finite State Machine Textbook Edition: 5.4, 5.5, 5.6 Second Third Edition: 5.5, 5.6, 5.7, C.3, C.4, C.5

2 functional units can be used only once per clock cycle duplication ) more silicon area ) different instructions have different CPI 9 3 CMPE Fall 26 A. Di Blas Multicycle CPU Drawbacks of single-cycle implementation CPI = for all instructions, but the clock cycle time is determined by the path worst-case SOLUTION: Multicycle implementation, with multiple cycles per instruction, but with shorter clock cycle time

3 try to balance the amount of work per stage 9 4 CMPE Fall 26 A. Di Blas Multicycle CPU Multicycle idea applied to our CPU PC I + D Memory IR Registers A ALU MDR B combinatorial block combinatorial block combinatorial block ALUOut ck

4 IR PC Addr Dout I+D Memory R_add Dout R_add2 CPU Registers W_add A ALU Din Dout2 B MDR Din Multicycle CPU High-level multicycle datapath ALUOut 9 5 CMPE Fall 26 A. Di Blas

5 9 6 CMPE Fall 26 A. Di Blas Multicycle CPU Differences from single-cycle datapath single memory for instructions and data (registers: IR and MDR) single ALU (registers: A and B) ALUOut register sharing functional units requires additional or expanded multiplexers The registers MDR, A, B, and ALUOut are written at every clock cycle.

6 PCW IorD IRWrite MemWrite MemRead RE WE IR PC Addr Dout I+D Memory Din MDR IR[25:] IR[25:2] IR[2:6] IR[5:] PC[3:] PC[3:28] << 2 RegDst A B 2 3 PCSource[:] J_add[3:] 2 3 Zero Res ALU sign extension << 2 ALU CTRL Multicycle CPU The complete multicycle CPU ALUOut R_add[4:] Dout R_add2[4:] W_add[4:] CPU Registers Dout2 Din WE RegWrite PC[3:] ALUSrcA 4 MemtoReg ALUSrcB[:] IR[5:] IR[5:] ALUop[:] Operation[2:] 9 7 CMPE Fall 26 A. Di Blas

7 IF Instruction Fetch get from memory instruction to execute ID Instruction Decode figure out what the instruction is EX EXecution or address calculation execute ALU operations MEM (Data) MEMory access if load/store, read/write memory WB Write Back write result/data from memory into destination register 9 8 CMPE Fall 26 A. Di Blas Multicycle CPU The execution steps

8 PC Memory Registers ALU Multicycle CPU IF Instruction Fetch Actions: IR = Memory[PC] // read instruction PC = PC + 4 // increment PC Control signals are the same for all instructions: PCW PCSource[:] IorD MemRead MemWrite IRWrite RegDest MemToReg RegWrite ALUsrcA ALUsrcB[:] Operation[2:] 9 9 CMPE Fall 26 A. Di Blas

9 PC Memory Registers ALU Multicycle CPU ID Instruction Decode Actions: A = Reg[IR[25:2]] // fetch operand A B = Reg[IR[2:6]] // fetch operand B ALUOut = PC + (sign-ex(ir[5:]) << 2) // comp. branch target Control signals are the same for all instructions: PCW PCSource[:] IorD MemRead MemWrite IRWrite RegDest MemToReg RegWrite ALUsrcA ALUsrcB[:] Operation[2:] 9 CMPE Fall 26 A. Di Blas

10 Arith./logic ALUOut = A op B Load/store ALUOut = A + sign-ex(ir[5:]) Branch if (A == B) PC = ALUOut Jump PC = (PC[3:28] << 28) (IR[25:] << 2) 9 CMPE Fall 26 A. Di Blas Multicycle CPU EXecution, memory address computation, branch EX or jump (/2) completion, Four different actions according to the instruction class:

11 PC Memory Registers ALU Multicycle CPU EXecution, memory address computation, branch EX or jump (2/2) completion, Four different sets of control signals according to the instruction class: INSTRUCTION CLASS PCW PCSource[:] IorD MemRead MemWrite IRWrite RegDest MemToReg RegWrite ALUsrcA ALUsrcB[:] Operation[2:] ARITH/L LD/STO BRANCH JUMP 9 2 CMPE Fall 26 A. Di Blas

12 Load MDR = Memory[ALUOut] Store Memory[ALUOut] = B PC Memory Registers ALU Multicycle CPU MEM MEMory access Two different actions according to whether it's a LOAD or a STORE. ONLY LOAD AND STORE INSTRUCTIONS HAVE A MEM STAGE! Two different sets of control signals: INSTRUCTION PCW PCSource[:] IorD MemRead MemWrite IRWrite RegDest MemToReg RegWrite ALUsrcA ALUsrcB[:] Operation[2:] LOAD STORE 9 3 CMPE Fall 26 A. Di Blas

13 Arith/Logic Reg[IR[5:]] = ALUOut Load Reg[IR[2:6]] = MDR PC Memory Registers ALU ARITH/L LOAD Multicycle CPU WB Write Back Two actions according to whether it's an ARITH/LOGIC or a LOAD: ONLY ARITH/LOGIC AND LOAD INS. HAVE A WB STAGE! INSTRUCTION CLASS PCW PCSource[:] IorD MemRead MemWrite IRWrite RegDest MemToReg RegWrite ALUsrcA ALUsrcB[:] Operation[2:] 9 4 CMPE Fall 26 A. Di Blas

14 9 5 CMPE Fall 26 A. Di Blas Multicycle CPU Instruction CPI in a multicycle CPU In a multicycle CPU, each instruction (instruction class) has its own CPI. Instruction Instr. class CPI add sub and or addi beq sw lw j

15 9 6 CMPE Fall 26 A. Di Blas Sequential control: FSM Control in a multicycle implementation Must have steps too! ) sequential control. Two main approaches: Finite State Machine (FSM) Microprogramming

16 conditions on the edges determine the next state 9 7 CMPE Fall 26 A. Di Blas Sequential control: FSM Example of Finite State Machine START 3 <cond> <outputs> <cond> <cond> <outputs> <cond> <outputs> <cond> <outputs> 2 <cond> 4 states outputs are associated with the states

17 9 8 CMPE Fall 26 A. Di Blas Sequential control: FSM outputs FSM implementation inputs present state future state ck Moore machine: the outputs are a function only of the state and not of the (current) inputs.

18 9 9 CMPE Fall 26 A. Di Blas Sequential control: FSM FSM control for our CPU START IF ID lw mem R mem addr comp 3 lw/sw 2 sw mem W 5 Arith beq j ALU EX branch jump 7 Res W WB 4 The outputs completely define the operation in each CPU step.

19 9 2 CMPE Fall 26 A. Di Blas Sequential control: FSM FSM control for arithmetic/logic instructions START MemRead ALUSrcA = IorD = IRWrite ALUSrcB = ALUOp = PCWrite PCSource = ALUSrcA = ALUSrcB = ALUOp = other RegDst = RegWrite MemtoReg = Arith/logic ALUSrcA = ALUSrcB = ALUOp =

20 PC Memory Registers ALU Sequential control: Microprogramming Microprogramming Idea: the control signals are the output of a (micro)program. The control word" looks like: Textbook format: Label ALU CTRL SRC SRC 2 Reg. CTRL Memory PC W Sequencing LABEL PCW PCSource[:] IorD MemRead MemWrite IRWrite RegDest MemToReg RegWrite ALUsrcA ALUsrcB[:] Operation[2:] SEQUENCING 9 2 CMPE Fall 26 A. Di Blas

21 9 22 CMPE Fall 26 A. Di Blas Sequential control: Microprogramming Example of microprogramming: Memory access Label ALU CTRL SRC SRC 2 Reg. CTRL Memory PC W Sequencing Fetch Add PC 4 - Read[PC] ALU Seq Add PC ExtShft Read - - Dispatch Mem Add A Extend Dispatch 2 lw Read[ALU] - Seq Write MDR - - Fetch sw Write[ALU] - Fetch

22 9 23 CMPE Fall 26 A. Di Blas Sequential control: Microprogramming Microprogramming implementation + Instr. Opcode Addr set µ PC Input Output datapath controls Microcode storage Sequencing ctrl

23 Exceptions: internal unexpected event Interrupts: external unexpected event 9 24 CMPE Fall 26 A. Di Blas Exceptions and Interrupts Exceptions and Interrupts Exceptions in our little CPU: arithmetic overflow undefined instruction

24 9 25 CMPE Fall 26 A. Di Blas Exceptions and Interrupts Exceptions handling It's the operating system's business. How does the OS distinguish among different causes of exceptions? Two approaches: interrupt vectors cause register (MIPS) the PC is saved in EPC, the cause register is set according to the cause of the exception, and the control is transferred to a fixed location in memory (e.g. xc )

25 I+D Memory sign extension A << ALU CTRL 3 Exceptions and Interrupts New schematic with exception handling Cause ALUOut PC PCW IorD IRWrite MemWrite MemRead Addr Din RE WE Dout IR MDR IR[25:] IR[25:2] IR[2:6] IR[5:] RegDst MemtoReg IR[5:] R_add[4:] R_add2[4:] W_add[4:] CPU Registers Din WE RegWrite Dout Dout2 PC[3:] PC[3:28] B PC[3:] ALUSrcA << 2 4 IR[5:] ALUop[:] J_add[3:] ALUSrcB[:] Zero Res OF ExcAddr Operation[2:] PCSource 2 IntCause EPCWrite CauseWrite EPC 9 26 CMPE Fall 26 A. Di Blas

26 9 27 CMPE Fall 26 A. Di Blas Exceptions and Interrupts New FSM control with exception handling START IF ID mem addr comp lw/sw 2 Arith ALU EX 6 beq branch 8 j other 9 jump exc= lw sw mem R 3 mem W 5 Res W 7 OF exc= 4 WB

27 9 28 CMPE Fall 26 A. Di Blas Recommended exercises Second Ed.: Ex. 5.3, 5.4, 5.5 to 5.2, 5.22 Third Ed.: Ex. 5.29, 5.3, 5.3, , 5.45