Orange Coast College. Business Division. Computer Science Department. CS 116- Computer Architecture. Pipelining

Transcription

1 Orange Coast College Business Division Computer Science Department CS 116- Computer Architecture Pipelining

2 Recall Pipelining is parallelizing execution Key to speedups in processors Split instruction execution into stages The Five Stages for MIPS execution Add memory to store state OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 2 2

3 Pipeline Hazards Hazard: Situation when next instruction cannot execute in the following clock cycle Types of Hazards Structural hazards Control hazards Data hazards OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 3 3

4 Structural Hazards Use the same resource in different ways at the same time and the hadware cannot support the combination Example: Use a single memory for instruction & data If we had more than 4 instructions, 1st instruction will be accessing data 4th instruction fetching the instruction Both need to access the memory in the same clock cycle Since MIPS was designed with two distinct memories, we don t encounter this problem => No hazards OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 4 4

5 Structural Hazards MIPS can easily avoid other structural hazards We can always resolve hazards by waiting pipeline control must detect the hazard take action (or delay action) to resolve hazards OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 5 5

6 Structural Hazards Single Memory is a Structural Hazard Time (clock cycles) I n s t r. O r d e r Load Instr 1 Instr 2 Instr 3 Instr 4 ALU Mem Reg Mem Reg ALU Mem Reg Mem Reg Mem ALU Mem Reg Mem Reg ALU Reg Mem Reg ALU Mem Reg Mem Reg Two memory accesses: If the same memory is used OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 6 6

7 Control Hazards Attempt to make a decision, based on the result of one instruction, before condition is evaluated (Caused in the branch instruction) First solution: Pipeline stall (Bubble) Pause (Wait) before continuing the pipeline, until the decision is clear calculate the branch address, update PC during the second stage OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 7 7

8 Control Hazards First solution: Pipeline stall (Bubble) Next instruction halts until condition result is known Like a no-operation is inserted in the 3rd step Next instruction will be executed in 4th step P rogram ex ecution order (in instructions) add $4, $5, $6 T im e Instruction fetch R eg A L U D ata access R eg beq $1, $2, 40 2ns Instruction fetch R eg A L U D ata access R eg lw $3, 300($0) bu bble 4 ns This period has no fetch [bubble) 4 seconds only after adding the extra HW Instruction fetch OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 8 8 2ns R eg A L U D ata access R eg

9 Control Hazards Disadvantages of first solution (Stall) Stall slows down the pipeline Second solution: Predict Guess one direction, then backup if wrong Always predict that branch will fail If you are right, pipeline proceeds at full speed (1 clock cycle) If you are wrong, Do pipeline stall(2 clock cycles) OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 9 9

10 Reduce Delay of Branches IF.Flus h Move branch execution earlier in pipeline Test beq condition using XOR instead of subtraction Faster since no carry is required M ux H az ar d det e cti o n u ni t I D / E X W B E X / M E M C ontr ol 0 M u x M W B M EM / W B IF /I D E X M WB PC 4 Instr ucti on me mor y S hift left 2 R eg ist er s = M u x A L U D at a m e m or y M ux M ux Sig n exte nd M ux F or w ar ding u nit OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 10 10

11 Control Hazards Second solution: Predict (fig. 6.50) For beq, the branch decision is done at cycle 4. The 3 following instructions will be fetched & begin execution If branch is not performed, no time is lost (no stall) If the branch should be performed, these instructions have to be flushed Flushing usually replaces the instruction with nop instruction P r o g ra m e x e c u tio n o r d e r ( in in s tr u c t io n s ) T im e (in c l o c k c y c le s ) C C 1 C C 2 C C 3 C C 4 C C 5 C C 6 C C 7 C C 8 C C b e q $ 1, $ 3, 72 IM R e g D M R e g 4 4 a n d $ 1 2, $ 2, $ 5 IM R e g D M R e g 4 8 o r $ 1 3, $ 6, $ 2 IM R e g D M R e g 5 2 a d d $ 1 4, $ 2, $ 2 IM R e g D M R e g 7 2 lw $ 4, 5 0 ($ 7 ) I M R e g D M R e g OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 11 11

12 Control Hazards Second solution: Predict Pipeline when branch is not taken No time is wasted Progr am execution order (in instructions) add $4, $5, $6 Time Instruction fetch Reg ALU Data access Reg beq $1, $2, 40 2 ns Instruction fetch Reg ALU Data access Reg lw $3, 300($0) 2 ns Instruction fetch Reg ALU Data access Reg OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 12 12

13 Control Hazards Second solution: Predict When branch is taken 2 ns wasted Moved test branch decision in 2nd stage Program execution order (in instructions) add $4, $5,$6 Time Instruction fetch Reg ALU Data access Reg beq $1, $2, 40 2 ns Instruction fetch Reg ALU Data access Reg bubble bubble bubble bubble bubble or $7, $8, $9 4 ns Instruction fetch Reg ALU Data access Reg OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 13 13

14 Control Hazards Disadvantage of second solution (Predict) Rigid and does not account for the specific branches Third solution: Dynamic Branch Prediction Guess depending on previous behavior of branch If right, pipeline proceeds at full speed If wrong, do pipeline stall and change prediction for next time Prediction changes over the lifetime of the program Prediction hardware has ~90% accuracy Cost of mis-prediction is higher OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 14 14

15 Control Hazards Fourth solution: Delayed branch Operation Always execute next instruction immediately after branch instruction, that dependent on the branch, or Try to execute branch first and delay next instruction This is not visible to the programmer Compilers fill ~50% of delays with useful instructions Instructions switched Program execution order (in instructions) beq $1, $2, 40 add $4, $5, $6 (Delayed branch slot) lw $3, 300($0) Time Instruction fetch 2 ns Reg Instruction fetch 2 ns OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) AL U Reg Instruction fetch 2 ns Data access ALU Reg Reg Data access AL U Reg Data access Reg

16 Data Hazards Problem: Instruction depends on the result of previous instruction still in the pipeline Attempt to use an item before it is ready Solution: Forwarding (Bypassing): Supply the needed intermediate results to the next instruction s stages as soon as they are evaluated Get the item early from the internal resources Forwarding: Result is passed forward from an earlier to a later instruction Bypassing: Passing the result by the register file to the desired unit OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 16 16

17 Data Hazards- Dependencies Progra m exe cution order (in instructions) Time (in clock cycles) Value of registe r $2: sub $2, $1, $3 CC 1 CC 2 CC 3 CC 4 CC 5 C C 6 IM Reg CC 7 CC 8 CC / DM Reg and $12, $2, $5 IM Reg DM R eg or $13, $6, $2 IM Reg D M Reg add $14, $2, $2 IM Reg DM Reg sw $15, 100($2) IM R eg DM Reg Backward dependencies are data hazards Forward dependencies are not hazards OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 17 17

18 Data Hazards- Dependencies Example: Problem with starting next instruction before first is finished sub instruction writes into $S2 All following instructions read $S2 Proper value is unavailable until the register is written (in cycle 5) Dependencies that go backward in time are data hazards OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 18 18

19 Data Hazards Example: add $s0, $t0, $t1 sub $t2, $s0, $t3 The subtract instruction immediately uses $s0 that is filled by the add instruction The add instruction doesn t write the result until the 5th stage Without intervention, a data hazard could severely stall the pipeline Solution: As soon as the ALU creates the sum for the add, forward it as an input for the subtract OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 19 19

20 Data Hazards Forwarding Only valid if the destination stage is later in time than the source stage Output of ALU (EX) of add instruction is forwarded to the input of ALU stage for sub instruction Program execution order Time (in instructions) add $s0, $t0, $t IF ID EX MEM WB sub $t2, $s0, $t3 IF ID EX MEM WB OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 20

21 Forwarding For some instruction types, we need to stall even with forwarding When an R-format instruction comes immediately after a load instruction This is done to prevent backward dependencies Program Time execution order (in instructions) lw $s0, 20($t1) IF ID EX MEM WB bubble bubble bubble bubble bubble sub $t2, $s0, $t3 IF ID EX MEM WB OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 21 21

22 Forwarding Without bubble: Backward (Data hazard) Program Time execution order (in instructions) lw $s0, 20($t1) IF ID EX MEM WB sub $t2, $s0, $t3 With bubble: Forward (No hazard) Program Time execution order (in instructions) lw $s0, 20($t1) IF ID EX MEM WB IF ID EX MEM WB bubble bubble bubble bubble bubble sub $t2, $s0, $t3 IF ID EX MEM WB OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 22

23 Forwarding Solution: Supply inputs to ALU by forwarding results as soon as they are evaluated Don t wait for the result to be written into register file Register file forwarding Handles read/write to same register ALU forwarding OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 23

24 Forwarding Example: $s2 will have 10 at the beginning and -20 at the end of cycle T i me (in c l ock cyc l es) Va l ue of register $2 : CC 1 CC 2 CC 3 CC 4 CC 5 CC 6 CC 7 CC 8 CC 9 Value of EX/MEM : Value of MEM/WB : X X X 20 X X X X X Program execution order X (in instruction) X X X 20 X X X X sub $2, $1, $3 IM Reg DM Reg and $12, $2, $5 IM Reg DM Reg or $13, $6, $2 IM Reg DM Reg add $14, $2, $2 IM Reg DM Reg sw $15, 100($2) Pipeline registers used to forward data IM Reg DM Reg OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 24

25 Improving Performance Exercise: For the following code that resembles a swap procedure: # $t1 = Addr v[k] lw $t0, 0($t1) # $t0(temp)= v[k] lw $t2, 4($t1) # $t2 = v[k+1] sw $t2, 0($t1) # v[k] = $t2 sw $t0, 4($t1) #v[k+1]= $t0 Draw the pipeline Find the hazards in this code Find out how can to reorder these instructions to avoid stalls OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 25

26 Improving Performance What about this order? # $t1 = Addr v[k] lw $t0, 0($t1) # $t0(temp)= v[k] lw $t2, 4($t1) # $t2 = v[k+1] sw $t0, 4($t1) #v[k+1]= $t0 sw $t2, 0($t1) # v[k] = $t2 On a machine with forwarding, the reordered sequence will take 4 clock cycles OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 26

27 Recent Trends in Performance Super-pipelining Super-scalar Dynamic pipelining OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 27 27

28 Super-Pipelining Remember: Speedup is related to # stages Idea: Make longer pipelines (more stages) Rebalance remaining steps so they are the same length Example: laundry Divide washing into: wash, rinse, & spin => 6 stages instead of 4 Recent microprocessors have >= 8 stages OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 28

29 Super-Scalar Idea: Replicate internal components to launch multiple instructions at the same time Effect: Instruction execution rate exceeds clock rate (CPI < 1) Example: laundry 3 washers 3 dryers 3 assistants to fold 3 assistants to put away laundry Example: Vote count OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 29

30 Super-Scalar Today s super-scalar computers have 2-6 instructions in every pipeline stage Problem: Difficult to implement if the instruction stream is dependent or doesn t meet the criteria OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 30

31 Super-Scalar MIPS Assumptions 2 instructions issued per clock cycle ALU/Branch instruction, in parallel with Load/Store instruction Need to fetch & decode 64 bits of instructions We examine the instructions & possibly swap them before sending them to the ALU or memory unit to reduce hazards Need extra HW OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 31 31

32 Super-Scalar MIPS Need extra hardware: Separate ALU for address calculation M ux M ux 4 ALU PC Instruction memory Registers M ux Write data Data memory Sign extend Sign extend ALU Address M ux OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 32

33 Super-Scalar MIPS Example Example(page 513) Loop: lw addu sw addi bne $t0, 0($s1) $t0, $t0,$s2 $t0, 0($s1) $s1, $s1,-4 $s1, $zero, Loop Assumption: $s1 contains +16 => Loop iterates 4 times 5 instructions (each needs 4 cycles) Original number of cycles needed = 5 * 4 =20 cycles Exercise: Draw the pipeline for the 4 iterations OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 33

34 Super-Scalar MIPS Example When adding another ALU => CPI should be ~.5 4 cycles per loop iteration Number of cycles = 4 * 4 = 16 => CPI (Performance) = 16/20 =0.8 => CPI value far from optimal ALU / Branch Data Transfer Instruction cycle Loop: lw $t0, 0($s1) 1 addi $s1, $s1, -4 2 addu $t0, $t0, $s2 3 bne $s1, $zero, Loop sw, $t0, 4($s1) 4 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 34

35 Super-Scalar MIPS Loop Unrolling Example Multiple copies of the body of the loop are made Different iterations are scheduled together Code in Super-scalar MIPS with loop unrolling: (4 copies of loop body) 12 out of 14 instructions work in super-scalar mode Total number of cycles = 8 CPI (Performance) = 8/20=0.4 => Better performance OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 35

36 Loop Unrolling Example Loop: addi $s1, $s1, -16 lw $t0, 0($s1) 1 lw $t1, 12($s1) 2 addu $t0, $t0, $s2 lw $t2, 8($s1) 3 addu $t1, $t1, $s2 lw $t3, 4($s1) 4 addu $t2, $t2, $s2 sw, $t0, 0($s1) 5 addu $t3, $t3, $s2 sw, $t1, 12($s1) 6 sw, $t2, 8($s1) 7 bne $s1, $zero, Loop sw, $t3, 4($s1) 8 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 36

37 Dynamic Pipelining Later instructions are executed while waiting for stall to be resolved Pipeline divided into 3 major units Instruction fetch & issue unit Send instructions in order Execution units Can execute in parallel (or out-of-order) Commit Unit Send instructions out in order again OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 37 37

38 Dynamic Pipelining Instruction fetch and decode unit In-order issue R eservation station R eservation station R eservation station R eservation station Execution Unit F unctional units Integer Integer F loating point Load/ Store O ut-of-order execute In-order commit Commit unit OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 38

39 Dynamic Pipelining Instruction fetch & issue unit: Fetches instructions Decodes instructions Send instruction to the corresponding functional unit Execution unit: 5-10 functional unit to hold operands & operators Each functional unit has a unit buffer (reservation station) When all operands are in the buffer & functional unit is ready, result is calculated Commit Unit: Decides when it is safe to put result back into register file or memory OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 39

40 Dynamic Pipelining The hardware performs the scheduling HW tries to find instructions to execute Out of order or parallel execution is possible Speculative execution: Combining dynamic scheduling & branch prediction OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 40

41 Dynamic Pipelining All modern processors are very complicated DEC Alpha 21264: 9 stage pipeline, 6 instruction issue PowerPC and Pentium: Branch history table Compiler technology is important as well as HW OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 41 41

42 Pentium Pro & PowerPC 604 pipeline organization PC Instruction cache Data cache Branch prediction Instruction queue Decode/dispatch unit Register file Reservation station Reservation station Reservation station Reservation station Reservation station Reservation station Branch Integer Integer Floating point Store Complex integer Load Load/ store Commit unit Reorder buffer OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 42

43 Summary Pipelining is a fundamental concept multiple steps using distinct resources Utilize capabilities of the Datapath by pipelined instruction processing start next instruction while working on the current one limited by length of longest stage (plus fill/sink) detect and resolve hazards OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 43

44 G4 Processor OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 44

45 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 45

46 Athlon Processor OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 46

47 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 47 47