Chapter 4. The Processor. Jiang Jiang

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1 Chapter 4 The Processor Jiang Jiang jiangjiang@ic.sjtu.edu.cn

2 [Adapted from Computer Organization and Design, 4 th Edition, Patterson & Hennessy, 2008, MK] Chapter 4 The Processor 2

3 Introduction CPU performance factors Instruction Count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations A simplified version A more realistic pipelined version A basic MIPS implementation Simple ISA subset, shows most aspects Memory reference: lw, sw Arithmetic/logical: add, sub, and, or, slt Control transfer: beq, j 4.1 Introduction Chapter 4 The Processor 3

4 Instruction Execution For all instructions, the first 2 steps are identical PC (instruction, Harvard) memory, fetch instruction Read one or two registers, using register numbers in fields of instruction register file, read registers Depending on instruction class, but the actions are largely the same Use ALU to calculate Arithmetic result Memory address for load/store Branch target address Access data memory for load/store PC target address or PC + 4 Simplicity favors regularity! Chapter 4 The Processor 4

5 CPU Overview Chapter 4 The Processor 5

6 Multiplexers Can t just join wires together Use multiplexers Chapter 4 The Processor 6

7 Control Chapter 4 The Processor 7

8 Logic Design Basics Information encoded in binary Low voltage = 0, High voltage = 1 One wire per bit Multi-bit data encoded on multi-wire buses Combinational element 4.2 Logic Design Conventions Operate on data Output is a function of input State (sequential) elements Store information Chapter 4 The Processor 8

9 Combinational Elements AND-gate Y = A && B Adder Y = A B A B + Y A B I0 I1 M u x S Y Multiplexer Y = S? I1 : I0 Y Arithmetic/Logic Unit Y = F(A, B) A ALU Y B F Chapter 4 The Processor 9

10 Sequential Elements Register: stores data in a circuit Uses a clock signal to determine when to update the stored value Edge-triggered: update when Clk changes from 0 to 1 D Clk Q Clk D Q Chapter 4 The Processor 10

11 Sequential Elements Register with write control Only updates on clock edge when write control input is 1 Used when stored value is required later Clk D Write Clk Q Write D Q Chapter 4 The Processor 11

12 Clocking Methodology Combinational logic transforms data during clock cycles Between clock edges Input from state elements, output to state element Longest delay determines clock period Chapter 4 The Processor 12

13 Building a Datapath Computer Organization Datapath, control, memory, Input, output Datapath Elements that operate on or hold data and addresses in the CPU Register file, ALUs, mux s, I/D memories, 4.3 Building a Datapath We will build a MIPS datapath incrementally Refining the overview design Chapter 4 The Processor 13

14 Instruction Fetch 32-bit register Increment by 4 for next instruction In MIPS, PC is affected only indirectly by certain instructions - it is NOT an architecturally-visible register Chapter 4 The Processor 14

15 R-Format Instructions Read two register operands (multi-port RF) Perform arithmetic/logical operation Write register result Chapter 4 The Processor 15

16 Load/Store Instructions Read register operands Calculate address using 16-bit offset Use ALU, but sign-extend offset to byte address! LW rt, offset(base) : lw $t0, 32($s3) Load: Read memory and update register Store: Write register value to memory Chapter 4 The Processor 16

17 Branch Instructions Read register operands beq $t0, $zero, L1 Compare operands Use ALU, subtract and check Zero output (?) Calculate target address Sign-extend displacement: 16b -> 32b Shift left 2 places (word displacement) Add to PC + 4 Already calculated by instruction fetch Reuse datapath with ld/st instructions Chapter 4 The Processor 17

18 Branch Instructions Just re-routes wires Sign-bit wire replicated Chapter 4 The Processor 18

19 Composing the Elements The simplest datapath executes an instruction in one clock cycle Each datapath element can only do one function at a time Hence, we need separate instruction and data memories (Harvard Architecture) Use multiplexers where alternate data sources are used for different instructions Chapter 4 The Processor 19

20 R-Type/Load/Store Datapath ld? ld/st? Chapter 4 The Processor 20

21 Full Datapath PC+4 Immediate/ Offset Chapter 4 The Processor 21

22 ALU Control Datapath + Control function ALU used for Load/Store: F = add Branch: F = subtract R-type: F depends on funct field ALU control Function 4.4 A Simple Implementation Scheme 0000 AND 0001 OR 0010 Add 0110 Subtract 0111 set-on-less-than 1100 NOR Chapter 4 The Processor 22

23 ALU Control Combinational logic derives ALU control Assume 2-bit ALUOp derived from opcode add:00, sub:01, determined by funct field: 10 Multiple levels of decoding 4-bit ALU control input ç 2-bit ALUOp field and 6-bit funct field opcode ALUOp Operation funct ALU function ALU control lw 00 load word XXXXXX add 0010 sw 00 store word XXXXXX add 0010 beq 01 branch equal XXXXXX subtract 0110 R-type 10 add add 0010 subtract subtract 0110 AND AND 0000 OR OR 0001 set-on-less-than set-on-less-than 0111 xxxxx: don t care Chapter 4 The Processor 23

24 The Main Control Unit Control signals derived from instruction Simplicity favors regularity! R-type 0 rs rt rd shamt funct 31:26 25:21 20:16 15:11 10:6 5:0 Load/ Store Branch 35 or 43 rs rt address 31:26 25:21 20:16 15:0 4 rs rt address 31:26 25:21 20:16 15:0 opcode always read, base for load/store read, except for load write for R-type and load sign-extend and add Chapter 4 The Processor 24

25 Datapath With Control opcode data of st ld? funct ld/st? ld? Chapter 4 The Processor 25

26 R-Type Instruction R-type Load/ Store Branch 0 rs rt rd shamt funct 31:26 25:21 20:16 15:11 10:6 5:0 35 or 43 rs rt address 31:26 25:21 20:16 15:0 4 rs rt address 31:26 25:21 20:16 15:0 opcode always read, base for load/store read, except for load write for R-type and load sign-extend and add Chapter 4 The Processor 26

27 R-Type Instruction Chapter 4 The Processor 27

28 Load Instruction R-type Load/ Store Branch 0 rs rt rd shamt funct 31:26 25:21 20:16 15:11 10:6 5:0 35 or 43 rs rt address 31:26 25:21 20:16 15:0 4 rs rt address 31:26 25:21 20:16 15:0 opcode always read, base for load/store read, except for load write for R-type and load sign-extend and add Chapter 4 The Processor 28

29 Load Instruction Chapter 4 The Processor 29

30 Branch-on-Equal Instruction R-type Load/ Store Branch 0 rs rt rd shamt funct 31:26 25:21 20:16 15:11 10:6 5:0 35 or 43 rs rt address 31:26 25:21 20:16 15:0 4 rs rt address 31:26 25:21 20:16 15:0 opcode always read, base for load/store read, except for load write for R-type and load sign-extend and add Chapter 4 The Processor 30

31 Branch-on-Equal Instruction Chapter 4 The Processor 31

32 Implementing Jumps Jump 2 address 31:26 25:0 Jump uses word address Update PC with concatenation of Top 4 bits of old PC 26-bit jump address 00 (word address to byte address) Need an extra control signal decoded from opcode Chapter 4 The Processor 32

33 Datapath With Jumps Added Chapter 4 The Processor 33

34 Performance Issues The single-cycle implementation is not practical Longest delay determines clock period Critical path: load instruction Instruction memory register file ALU data memory register file Not feasible to vary period for different instructions Violates design principle Making the common case fast We will improve performance by pipelining Chapter 4 The Processor 34

35 Pipelining Analogy Pipelined laundry: overlapping execution Parallelism improves performance Four loads: Speedup = 8/3.5 = 2.3 Non-stop: 4.5 An Overview of Pipelining Speedup = 2n/( n) 4 = number of stages n-1:1.5 Chapter 4 The Processor 35

36 Parallelism The most fundamental ways to improve performance Two types of parallelism Temporal parallelism Pipeline Less work per stage shorter clock cycle More penalty in control hazard and interruption Spatial parallelism Multiple function units, multiple cores Replicate resource, multiple issue, multicore Chapter 4 The Processor 36

37 MIPS Pipeline Five stages, one step per stage 1. IF: Instruction fetch from memory 2. ID: Instruction decode & register read 3. EX: Execute operation or calculate address 4. MEM: Access memory operand (load/store) 5. WB: Write result back to register Chapter 4 The Processor 37

38 Pipeline Performance Assume time for stages is 100ps for register read or write 200ps for other stages Compare pipelined datapath with single-cycle datapath Instr Instr fetch Register read Decode ALU op Memory access Register write Total time lw 200ps 100 ps 200ps 200ps 100 ps 800ps sw 200ps 100 ps 200ps 200ps 700ps R-format 200ps 100 ps 200ps 100 ps 600ps beq 200ps 100 ps 200ps 500ps Chapter 4 The Processor 38

39 Pipeline Performance Single-cycle (T c = 800ps) Pipelined (T c = 200ps) Chapter 4 The Processor 39

40 Pipelined Datapath Chapter 4 The Processor 40

41 Pipeline Speedup If all stages are balanced I.e., all take the same time Time between instructions pipelined = Time between instructions nonpipelined Number of stages If not balanced, speedup is less Speedup due to increased throughput Latency (time for each instruction) does not decrease Chapter 4 The Processor 41

42 Pipelining and ISA Design MIPS ISA designed for pipelining All instructions are 32-bits Easier to fetch in one cycle C.f. x86: 1- to 17-byte instructions Few and regular instruction formats Can decode and read registers in one step Load/store addressing Can calculate address in 3 rd stage, access memory in 4 th stage Alignment of memory operands Memory access takes only one cycle Chapter 4 The Processor 42

43 Pipeline Hazards Situations that prevent starting the next instruction in the next cycle 3 types of hazards Structure hazards A required resource is busy, e.g. memory Data hazard Need to wait for previous instruction to complete its data read/write (Producer-Consumer problem) Control hazard Deciding on control action depends on previous instruction, e.g. branch Chapter 4 The Processor 43

44 Structure Hazards Conflict for use of a resource In MIPS pipeline with a single memory Load/store requires data access Instruction fetch would have to stall for that cycle => Would cause a pipeline bubble Hence, pipelined datapath requires separate instruction/data memories Or separate instruction/data caches (L1I, L1D) Modified Von Neumann, cf. Harvard architecture Chapter 4 The Processor 44

45 Pipelined Datapath Chapter 4 The Processor 45

46 Data Hazards An instruction depends on completion of data access by a previous instruction add $s0, $t0, $t1 sub $t2, $s0, $t3 W R 5-2=3, 2 bubbles! Chapter 4 The Processor 46

47 Forwarding (aka Bypassing) Use result when it is computed Don t wait for it to be stored in a register Requires extra connections in the datapath No bubble! 4-3=1, no stall! Chapter 4 The Processor 47

48 Load-Use Data Hazard Can t always avoid stalls by forwarding If value not computed when needed Can t forward backward in time! IF ID EX 5-3=2, 1 bubble! Chapter 4 The Processor 48

49 Code Scheduling to Avoid Stalls Reorder code to avoid use of load result in the next instruction C code for A = B + E; C = B + F; stall stall lw $t1, 0($t0) lw $t2, 4($t0) add $t3, $t1, $t2 sw $t3, 12($t0) lw $t4, 8($t0) add $t5, $t1, $t4 sw $t5, 16($t0) 13 cycles lw $t1, 0($t0) lw $t2, 4($t0) lw $t4, 8($t0) add $t3, $t1, $t2 sw $t3, 12($t0) add $t5, $t1, $t4 sw $t5, 16($t0) 11 cycles Chapter 4 The Processor 49

50 Control Hazards Branch determines flow of control Fetching next instruction depends on branch outcome Pipeline can t always fetch correct instruction, so Stall on branch and wait for the outcome of branch, or Fetch next instruction (predict none-taken) and go In MIPS pipeline Need to compare registers and compute target earlier in the pipeline Add extra hardware to do it in ID stage (earliest? )... (I3) I2 I1... (?) I2? beq Chapter 4 The Processor 50

51 Stall on Branch Wait until branch outcome determined before fetching next instruction 1 bubble when determine in ID Is no stall possible? IF, prediction 3-1=2, 1 bubble! Chapter 4 The Processor 51

52 Branch Prediction Longer pipelines can t readily determine branch outcome early Stall penalty becomes unacceptable Predict outcome of branch in early stage Only flush pipeline if prediction is wrong As early as possible In MIPS pipeline (MIPS) Can predict branches not taken => sequential Fetch instruction after branch (PC+4), with no delay Where to predict? IF stage Where to compute outcome? ID stage or later Chapter 4 The Processor 52

53 MIPS with Predict Not Taken Prediction correct: reward 2-1=1, No bubble! Prediction incorrect: penalty lw $3, 300($0) flush lw inst. ID stage Chapter 4 The Processor 53

54 More-Realistic Branch Prediction Static branch prediction Based on typical branch behavior Example: loop and if-statement branches Predict backward branches taken Predict forward branches not taken Dynamic branch prediction Hardware measures actual branch behavior E.g., record recent history of each branch Assume future behavior will continue the trend When wrong, flush and re-fetching, and update history More than 90% accuracy Chapter 4 The Processor 54

55 Pipeline Summary The BIG Picture Pipelining improves performance by increasing instruction throughput Executes multiple instructions in parallel Each instruction has the same latency Subject to hazards Structure, data, control Instruction set design affects complexity of pipeline implementation Chapter 4 The Processor 55

56 MIPS Pipelined Datapath 4.6 Pipelined Datapath and Control Right-to-left flow leads to hazards WB Chapter 4 The Processor 56

57 Pipeline registers Need pipeline registers between stages To hold information produced in previous cycle Chapter 4 The Processor 57

58 Pipeline Operation Diagram Cycle-by-cycle flow through the pipelined datapath Single-clock-cycle pipeline diagram Snapshot of pipeline usage in a single cycle Temporal parallelism Highlight resources used multi-clock-cycle diagram Graph of operation over time Chapter 4 The Processor 58

59 Pipeline Operation Diagram We highlight the right half of registers or memory when they are being read and highlight the left half when they are being written We ll look at single-clock-cycle diagrams for load & store W R Chapter 1 Computer Abstractions and Technology 59

60 IF for Load, Store, W R Chapter 4 The Processor 60

61 ID for Load, Store, Chapter 4 The Processor 61

62 EX for Load Chapter 4 The Processor 62

63 MEM for Load Chapter 4 The Processor 63

64 WB for Load Wrong register number Chapter 4 The Processor 64

65 Corrected Datapath for Load Instruction[20-16] Chapter 4 The Processor 65

66 EX for Store Chapter 4 The Processor 66

67 MEM for Store Chapter 4 The Processor 67

68 WB for Store Chapter 4 The Processor 68

69 Multi-Cycle Pipeline Diagram Form showing resource usage Temporal parallelism M M Chapter 4 The Processor 69

70 Single-Cycle Pipeline Diagram State of pipeline in a given cycle Chapter 4 The Processor 70

71 Pipelined Control (Simplified) Why used here? st data ld? 32 ld/st? ld? Chapter 4 The Processor 71

72 Pipelined Control Control signals derived from instruction As in single-cycle implementation Instruction[31-26] Chapter 4 The Processor 72

73 The Main Control Unit Control signals derived from instruction R-type Load/ Store Branch 0 rs rt rd shamt funct 31:26 25:21 20:16 15:11 10:6 5:0 35 or 43 rs rt address 31:26 25:21 20:16 15:0 4 rs rt address 31:26 25:21 20:16 15:0 opcode always read, base for load/store read, except for load write for R-type and load sign-extend and add Chapter 4 The Processor 73

74 Pipelined Control 32 ld? Why not select in ID stage? Chapter 4 The Processor 74

75 Data Hazards in ALU Instructions Consider this sequence sub $2, $1,$3 and $12,$2,$5 or $13,$6,$2 add $14,$2,$2 sw $15,100($2) We can alleviate hazards by 2 means Data forwarding from preceding instructions Read and write a register in the same cycle 4.7 Data Hazards: Forwarding vs. Stalling Chapter 4 The Processor 75

76 Dependencies & Forwarding Alternatively, Reg Value is available here Inner-register forwarding Chapter 4 The Processor 76

77 Register File Access Hazard Fix register file access hazard Write in the first half of the cycle and Read in the second half Read and write a register in the same cycle => no data hazard It s the case for many implementation of register file Chapter 1 Computer Abstractions and Technology 77

78 Register File Access? Time (clock cycles) I n s t r. sub $2, Inst ALU IM Reg DM Reg 4 ALU IM Reg DM Reg 5 6 Alternatively, Reg Value is available here O r d e r Inst 3 add $14,$2, ALU IM Reg DM Reg ALU IM Reg DM Reg 5.5 clock edge that controls the register file writing clock edges that control the pipeline registers writing

79 Detecting the Need to Forward Pass register numbers along pipeline E.g., ID/EX.RegisterRs = register number for Rs sitting in ID/EX pipeline register ALU (consumer) operand register numbers in EX stage are given by ID/EX.RegisterRs, ID/EX.RegisterRt Data hazards when Bypassing from two stages to ID/EX 1a. EX/MEM.RegisterRd = ID/EX.RegisterRs 1b. EX/MEM.RegisterRd = ID/EX.RegisterRt 2a. MEM/WB.RegisterRd = ID/EX.RegisterRs 2b. MEM/WB.RegisterRd = ID/EX.RegisterRt Fwd from EX/MEM pipeline reg Fwd from MEM/WB pipeline reg Chapter 1 Computer Abstractions and Technology 79

80 Forwarding Paths ld? Why here? Chapter 4 The Processor 80

81 Detecting the Need to Forward But only if forwarding instruction will write to a register! EX/MEM.RegWrite, MEM/WB.RegWrite And only if Rd for that instruction is not $zero (why?) EX/MEM.RegisterRd 0, MEM/WB.RegisterRd 0 Chapter 4 The Processor 81

82 Forwarding Conditions EX hazard (forwarding from EX/MEM register) if (EX/MEM.RegWrite and (EX/MEM.RegisterRd 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRs)) ForwardA = 10 if (EX/MEM.RegWrite and (EX/MEM.RegisterRd 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRt)) ForwardB = 10 MEM hazard (forwarding from MEM/WB register) if (MEM/WB.RegWrite and (MEM/WB.RegisterRd 0) and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA = 01 if (MEM/WB.RegWrite and (MEM/WB.RegisterRd 0) and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB = 01 Chapter 4 The Processor 82

83 Double Data Hazard Consider the sequence: add $1,$1,$2 add $1,$1,$3 add $1,$1,$4 Both hazards occur ;instr 1 in WB ;instr 2 in MEM ;instr 3 in EX Want to use the most recent value (closest producer instruction) I.e. instruction 3 should get the value forwarding from instruction 2 (EX/MEM), not instruction 1 (MEM/WB) Revise MEM hazard condition (forwarding from WB Stage) Only forwd if EX hazard condition isn t true Chapter 4 The Processor 83

84 Revised Forwarding Condition MEM hazard (forwarding from MEM/WB register) if (MEM/WB.RegWrite and (MEM/WB.RegisterRd 0) and not (EX/MEM.RegWrite and (EX/MEM.RegisterRd 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRs)) and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA = 01 if (MEM/WB.RegWrite and (MEM/WB.RegisterRd 0) and not (EX/MEM.RegWrite and (EX/MEM.RegisterRd 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRt)) and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB = 01 Chapter 4 The Processor 84

85 Datapath with Forwarding RegWrite RegWrite ld -> Rt Chapter 4 The Processor 85

86 Load-Use Data Hazard Need to stall for one cycle 5-3=2, 1 bubble! Chapter 4 The Processor 86

87 Load-Use Hazard Detection Check load-use hazard in ID stage (why?) Where to stall and insert bubble? ALU operand register numbers in ID stage are given by IF/ID.RegisterRs, IF/ID.RegisterRt: consumers Load-use hazard when ID/EX.MemRead and ((ID/EX.RegisterRt = IF/ID.RegisterRs) or (ID/EX.RegisterRt = IF/ID.RegisterRt)) Load/ Store 35 or 43 rs rt address 31:26 25:21 20:16 15:0 Chapter 4 The Processor 87

88 Load-Use Hazard Detection If the load-use hazard detected 1 st cycle: stall and insert bubble from ID to EX stage in the 1 st cycle (current cycle), keep the use instruction in ID stage 2 nd cycle: the EX stage is a bubble in the 2 nd cycle è 1 bubble Load instruction is in MEM now 3 rd cycle: let the current use instruction go to EX stage in the 3 rd cycle, and forward the load data from EX/MEM to EX stage Load instruction is in WB now Chapter 4 The Processor 88

89 Load-Use Hazard Detection 1 st 2 nd 3 rd Keep! Chapter 4 The Processor 89

90 How to Stall the Pipeline Force control values in ID/EX register to 0 Check in ID stage, and insert bubble into EX stage EX, MEM and WB do nop (no-operation) Prevent update of PC and IF/ID register Keep current instruction in IF/ID, next instruction is PC Using (Current) instruction is decoded again Following instruction is fetched again (by same PC) 1-cycle stall allows MEM to read data for lw Can subsequently forward to EX stage in next cycle Alternative: valid signal for each instruction? Chapter 4 The Processor 90

91 Datapath with Hazard Detection Checking Forwarding ld instr s Rt, Instruction[20-16] ID/EX.RegisterRt Chapter 4 The Processor 91

92 Datapath with Hazard Detection Stall! ld instr s Rt, Instruction[20-16] Chapter 4 The Processor 92

93 Stall/Bubble in the Pipeline Check here: ID Bubble inserted here: ID Forward here: EX, from MEM/WB Or, more accurately Chapter 4 The Processor 93

94 Stalls and Performance The BIG Picture Stalls reduce performance But are required to get correct results Compiler can rearrange code to avoid hazards and stalls Requires knowledge of the pipeline structure Data hazard doesn t occur (no stalls) when For instructions: i (producer),..., j (consumer) InstrSeqNum(j) - InstrSeqNum(i) EarliestDataValidStageNum(i) - DataUseStageNum(j) Chapter 4 The Processor 94

95 Branch Hazards If branch outcome determined in MEM (why?) Compute in EX Assume branch Not Taken => pc + 4, fall-through 4.8 Control Hazards 5-1 =4, 3 bubble! Flush 3 instructions (Set control values to 0), or clear the valid signal Chapter 4 The Processor 95

96 Datapath and Control Chapter 4 The Processor 96

97 Reducing Branch Delay Move hardware to determine outcome to ID stage (why?) Target address adder Register comparator The outcome is sent to the mux before PC at the same cycle (2 nd cycle), but takes effect in next cycle (3 rd cycle) The earlier, the better Determine in ID => 1 bubble (3 1 = 2) Can it be moved before ID? Example: branch taken 36: sub $10, $4, $8 40: beq $1, $3, 7 ;if taken, what addr? 44: and $12, $2, $5 48: or $13, $2, $6 52: add $14, $4, $2 56: slt $15, $6, $ : lw $4, 50($7) Chapter 4 The Processor 97

98 Example: Branch Taken-clk IF.Flush 3 1=2, 1 bubble Flush: bubble inserted here, Zero è nop Chapter 4 The Processor 98

99 Example: Branch Taken-clk 4 Chapter 4 The Processor 99

100 Delayed Branches If the branch hardware has been moved to the ID stage, then we can eliminate all branch stalls with delayed branches Always executing the next sequential instruction after the branch instruction No flush for IF/ID The branch takes effect after that next instruction MIPS compiler moves an instruction to immediately after the branch that is NOT affected by the branch (a safe instruction) thereby hiding the branch delay Chapter 1 Computer Abstractions and Technology 100

101 Delayed Branches IF.Flush No flush: current instr. will be executed definitely Chapter 4 The Processor 101

102 Scheduling Branch Delay Slots A. From before branch B. From branch target C. From fall through add $1,$2,$3 if $2=0 then delay slot sub $4,$5,$6 add $1,$2,$3 if $1=0 then delay slot add $1,$2,$3 if $1=0 then delay slot sub $4,$5,$6 becomes becomes becomes if $2=0 then add $1,$2,$3 add $1,$2,$3 if $1=0 then sub $4,$5,$6 add $1,$2,$3 if $1=0 then sub $4,$5,$6 Chapter 1 Computer Abstractions and Technology 102

103 Data Hazards for Branches If a comparison register is a destination of 2 nd or 3 rd preceding ALU instruction add $1, $2, $3 IF ID EX MEM WB add $4, $5, $6 IF ID EX MEM WB IF ID EX MEM WB beq $1, $4, target IF ID EX MEM WB Can resolve using forwarding 3 (InstrDistance(1 st add, beq)) 2 (4 (MEM) - 2 (ID)), no stall 2 (InstrDistance(2 nd add, beq)) 2 (4 (MEM) - 2 (ID)), no stall Chapter 4 The Processor 103

104 Data Hazards for Branches If a comparison register is a destination of immediately preceding load instruction Need 2 stall cycles 1 (InstrDistance(lw, beq)) < 3 (5 (WB) - 2 (ID)), 2 stall lw $1, addr IF ID EX MEM WB beq stalled IF ID beq stalled ID beq $1, $0, target ID EX MEM WB Chapter 4 The Processor 104

105 Data Hazards for Branches If a comparison register is a destination of preceding ALU instruction or 2 nd preceding load instruction Need 1 stall cycle 2 (InstrDistance(lw, beq)) < 3 (5 (WB) - 2 (ID)), 3-2 = 1 stall 1 (InstrDistance(add, beq)) < 2 (4 (MEM) - 2 (ID)), 2-1 = 1 stall lw $1, addr IF ID EX MEM WB add $4, $5, $6 IF ID EX MEM WB beq stalled IF ID beq $1, $4, target ID EX MEM WB Chapter 4 The Processor 105

106 Dynamic Branch Prediction In deeper and superscalar pipelines, branch penalty is more significant Calculate branch outcome in a later pipeline stage The earlier, the better è extra hardware è guess Use dynamic prediction Normally in 1 st stage (IF) Prediction in earlier stage and verification in outcome calculating stage Even with predictor, still need to calculate the target address Where in MIPS? ID stage: read register for calculation 1-cycle penalty for a taken branch: address used in IF stage 3 1 = 2 Chapter 4 The Processor 106

107 Dynamic Branch Prediction Branch prediction buffer (branch history table) Stores outcome (taken/not taken) Indexed by recent branch instruction addresses Normally, by the lower portion of the branch address To execute a branch Check table, expect the same outcome Start fetching from fall-through or target If wrong, flush pipeline and flip prediction Where to verify in MIPS? (ID stage?) Can calculate the target address in a later stage If use branch prediction, no need for delayed branch Chapter 4 The Processor 107

108 1-Bit Predictor Inner loop branches mispredicted twice! outer: inner: beq,, inner beq,, outer Mispredict as taken on last iteration of inner loop The current state is T! Then mispredict as not taken on first iteration of inner loop next time around The current state is NT! Chapter 4 The Processor 108

109 2-Bit Predictor Only change prediction on two successive mispredictions Mispredicted only once Mispredict as taken on last iteration of inner loop Chapter 4 The Processor 109

110 Branch Target Buffer Cache of target addresses C.f. store outcome in branch prediction/history buffer Indexed by PC when instruction fetched If hit and instruction is branch predicted taken, can fetch target immediately Can be done in IF stage (why?) No penalty if prediction is correct How about the penalty if wrong? Depends on where to compute the outcome Chapter 4 The Processor 110

111 The Final Datapath and Control Load-Use Hazard Branch Hazard Chapter 1 Computer Abstractions and Technology 111

112 Exceptions and Interrupts Unexpected events requiring change in flow of control Different ISAs use the terms differently Normally, two types 4.9 Exceptions Exception/Trap: arises within the CPU E.g., undefined opcode, overflow, syscall, Interrupt: from external devices E.g., I/O controller In IA-64, interruption = exception + interrupt Dealing with them without sacrificing performance is hard Chapter 4 The Processor 112

113 ISA and Exception Some languages (e.g., C) ignore overflow Use MIPS addu, addiu, subu instructions Other languages (e.g., Ada, Fortran) require raising an exception Use MIPS add, addi, sub instructions addu add Operation: if (NotWordValue(GPR[rs]) or NotWordValue(GPR[rt])) then UndefinedResult() endif temp GPR[rs] + GPR[rt] GPR[rd] sign_extend(temp ) Exceptions: None Operation: if (NotWordValue(GPR[rs]) or NotWordValue(GPR[rt])) then UndefinedResult() endif temp GPR[rs] + GPR[rt] if (32_bit_arithmetic_overflow) then SignalException(IntegerOverflow) else GPR[rd] sign_extend(temp ) endif Exceptions: Integer Overflow Chapter 3 Arithmetic for Computers 113

114 Handling Exceptions In MIPS, exceptions managed by a System Control Coprocessor (CP0) CP0 provides the processor control, memory management, and exception handling functions C.f. FP is coprocessor 1 (CP1) mfc0 (move from coprocessor 0 s reg) instruction can retrieve EPC value, to return after corrective action Chapter 4 The Processor 114

115 Handling Exceptions For the OS to handle the exception, HW Save PC of offending (or interrupted) instruction In MIPS: Exception Program Counter (EPC) Save indication of the problem In MIPS: using status register Cause Register We ll assume 1-bit 0: undefined instruction 1: arithmetic overflow Jump to predefined handler (single entry point) at hex Chapter 4 The Processor 115

116 An Alternative Mechanism Vectored Interruption Handler address determined by the cause Normally by hardware Example: Undefined opcode: C Overflow: C : C Instructions at handler address either Deal with the exception, or Jump to real handler Chapter 4 The Processor 116

117 Handler Actions Read cause, and transfer to relevant handler Determine action required If restartable Take corrective action Use EPC to return to program Otherwise Terminate program Report error using EPC, cause, Chapter 4 The Processor 117

118 Exceptions in a Pipeline Another type of control hazard Consider overflow on add in EX stage add $1, $2, $1 Prevent $1 from being clobbered Complete preceding instructions Flush add (current) and subsequent instructions Set Cause and EPC register values Transfer control to handler (how?) Similar to mispredicted branch Use much of the same hardware Chapter 4 The Processor 118

119 Pipeline with Exceptions instr. 3 instr. 2 instr. 1 Load-Use Hazard exception address IF.Flush Flush to zero => nop Chapter 4 The Processor 119

120 Exception Properties Restartable exceptions Handler executes, then refetched and executed this instruction from scratch In IA-64 Exception: returns to current instruction Interrupt: returns to next instruction PC saved in EPC register Identifies causing instruction In MIPS, actually PC + 4 is saved (why?) SW handler must adjust Chapter 4 The Processor 120

121 Exception Example Exception on add in 40 sub $11, $2, $4 44 and $12, $2, $5 48 or $13, $2, $6 4C add $1, $2, $1 50 slt $15, $6, $7 54 lw $16, 50($7) Handler sw $25, 1000($0) sw $26, 1004($0) Chapter 4 The Processor 121

122 Exception Example generated by HW 50, why? PC = 4C Chapter 4 The Processor 122

123 Exception Example handler s instr. preceding instr. Chapter 4 The Processor 123

124 Multiple Exceptions Pipelining overlaps multiple instructions Could have multiple exceptions at the same time in different pipeline stages Simple approach: deal with exception from earliest instruction Flush subsequent instructions Precise exceptions In complex pipelines Multiple instructions issued per cycle Out-of-order completion Maintaining precise exceptions is difficult! Chapter 4 The Processor 124

125 Imprecise Exceptions Just stop pipeline and save state Including exception cause(s) Let the software handler work out Which instruction(s) had exceptions Which to complete or flush May require manual completion Simplifies hardware, but more complex handler software Not feasible for complex multiple-issue out-of-order pipelines Chapter 4 The Processor 125

126 Instruction-Level Parallelism (ILP) Pipelining: executing multiple instructions in parallel To increase ILP exploit parallelism Deeper pipeline (temporal parallelism) Less work per stage shorter clock cycle More penalty in control hazard and interruption Multiple function units (spatial parallelism) Replicate resource, multiple issue Multiple pipelines Replicate pipelines Spatial parallelism + temporal parallelism 4.10 Parallelism and Advanced Instruction Level Parallelism Chapter 4 The Processor 126

127 Multiple Issue Start multiple instructions per clock cycle Instructions Per Cycle (IPC) CPI < 1, so use IPC C.f. CPI in single pipeline E.g., 4GHz 4-way multiple-issue 16 BIPS, peak CPI = 0.25, peak IPC = 4 But dependencies reduce this in practice Structure, data, control hazard Chapter 4 The Processor 127

128 Multiple Issue Static multiple issue Compiler groups instructions to be issued together Packages them into issue packets Compiler detects dependencies and avoids hazards Dynamic multiple issue CPU examines instruction stream and chooses instructions to issue each cycle Compiler can help by reordering instructions CPU resolves hazards using advanced techniques at runtime Hybrid way: SW/HW synergy, e.g. IA-64 Chapter 4 The Processor 128

129 Speculation To improve performance Exploit parallelism Sole ILP è ILP, DLP, TLP, RLP Use prediction or speculation è ILP Guess what to do with an instruction Start operation as early as possible Check whether guess was right If so, complete the operation If not, roll-back and do the right thing Chapter 4 The Processor 129

130 Speculation Common to static and dynamic multiple issue Examples Speculate on branch outcome Roll back if path taken is different è flush and refetch Speculate on load Roll back if location is updated or exception occurs E.g., IA-64 data speculation and control speculation Chapter 4 The Processor 130

131 Compiler/Hardware Speculation Compiler can reorder instructions E.g., move load before branch Should include fix-up instructions to recover from incorrect guess Hardware can look ahead for instructions to execute Buffer results until it determines they are actually needed Flush buffers on incorrect speculation Energy saving? Chapter 4 The Processor 131

132 Speculation and Exceptions What if exception occurs on a speculatively executed instruction? E.g., speculative load before null-pointer check Static speculation Can add ISA support for deferring exceptions Dynamic speculation Can buffer/defer exceptions until instruction completion (which may not occur) Chapter 4 The Processor 132

133 Static Multiple Issue Compiler groups instructions into issue packets Group of instructions that can be issued on a single cycle no dependencies Determined by pipeline resources required Think of an issue packet as a very long instruction Specifies multiple concurrent operations Very Long Instruction Word (VLIW) Chapter 4 The Processor 133

134 Scheduling Static Multiple Issue Compiler must remove some/all hazards Reorder instructions into issue packets No dependencies within a packet Possibly some dependencies between packets Varies between ISAs; compiler must know! Pad with nop if necessary May increase instruction count significantly Chapter 4 The Processor 134

135 MIPS with Static Dual Issue Two-issue packets: two pipelines One ALU/branch instruction One load/store instruction 64-bit aligned (2 instruction word) ALU/branch first, then load/store In order to simplify the decoding and instruction issue Pad an unused instruction slot with nop Address Instruction type Pipeline Stages n ALU/branch IF ID EX MEM WB n + 4 Load/store IF ID EX MEM WB n + 8 ALU/branch IF ID EX MEM WB n + 12 Load/store IF ID EX MEM WB n + 16 ALU/branch IF ID EX MEM WB n + 20 Load/store IF ID EX MEM WB Chapter 4 The Processor 135

136 MIPS with Static Dual Issue extra RF port Load/Store Chapter 4 The Processor 136

137 Hazards in the Dual-Issue MIPS More instructions executing in parallel EX data hazard Forwarding avoided stalls with single-issue Now can t use ALU result in load/store in same packet add $t0, $s0, $s1 load $s2, 0($t0) Complier avoids all dependencies within a packet Split into two packets, a stall Load-use hazard Still one cycle use latency, but affects two instructions More aggressive scheduling required Chapter 4 The Processor 137

138 Scheduling Example Schedule this for dual-issue MIPS Loop: lw $t0, 0($s1) # $t0=array element addu $t0, $t0, $s2 # add scalar in $s2 sw $t0, 0($s1) # store result addi $s1, $s1, 4 # decrement pointer bne $s1, $zero, Loop # branch $s1!=0 ALU/branch Load/store cycle Loop: nop lw $t0, 0($s1) 1 addi $s1, $s1, 4 nop 2 addu $t0, $t0, $s2 nop 3 bne $s1, $zero, Loop sw $t0, 4($s1) 4 IPC = 5/4 = 1.25 (cf. peak IPC = 2) Chapter 4 The Processor 138

139 Loop Unrolling Replicate loop body to expose more parallelism Reduces loop-control overhead Use different registers per replication Called register renaming Avoid loop-carried anti-dependencies Store (r) followed by a load (w) of the same register (WAR) Aka name dependence Reuse of a register name Three cases of dependency True (data) dependence Anti-dependence Output dependence Chapter 4 The Processor 139

140 Loop Unrolling Example ALU/branch Load/store cycle Loop: addi $s1, $s1, 16 lw $t0, 0($s1) 1 nop lw $t1, 12($s1) 2 addu $t0, $t0, $s2 lw $t2, 8($s1) 3 addu $t1, $t1, $s2 lw $t3, 4($s1) 4 addu $t2, $t2, $s2 sw $t0, 16($s1) 5 addu $t3, $t4, $s2 sw $t1, 12($s1) 6 nop sw $t2, 8($s1) 7 bne $s1, $zero, Loop sw $t3, 4($s1) 8 IPC = 14/8 = 1.75 Closer to 2, but at cost of registers and code size Chapter 4 The Processor 140

141 Dynamic Multiple Issue Superscalar processors: multiple pipelines CPU decides whether to issue 0, 1, 2, each cycle Issue criterion Avoid structural and data hazards Must in-order issue! Code semantics ensured by the CPU Avoids the need for compiler scheduling Though it may still help Chapter 4 The Processor 141

142 Dynamic Pipeline Scheduling Allow the CPU to execute instructions out of order to avoid stalls But commit result to registers in order Example lw $t0, 20($s2) addu $t1, $t0, $t2 sub $s4, $s4, $t3 slti $t5, $s4, 20 Can execute sub while addu is waiting for lw Chapter 4 The Processor 142

143 Dynamically Scheduled CPU Preserves dependencies Hold pending operands Results also sent to any waiting reservation stations Reorders buffer for register writes Can supply operands for issued instructions Chapter 4 The Processor 143

144 Register Renaming Reservation stations and reorder buffer effectively provide register renaming On instruction issue to reservation station If operand is available in register file or reorder buffer Copied to reservation station No longer required in the register; can be overwritten If operand is not yet available It will be provided to the reservation station by a function unit Register update may not be required Chapter 4 The Processor 144

145 Speculation Predict branch and continue issuing Don t commit until branch outcome determined Load speculation Advantage: avoid load and cache miss delay Predict the effective address Predict loaded value Load before completing outstanding stores Bypass stored values to load unit Don t commit load until speculation cleared Chapter 4 The Processor 145

146 Why Do Dynamic Scheduling? Why not just let the compiler schedule code? Not all stalls are predicable E.g., cache misses Can t always schedule around branches Branch outcome is dynamically determined Different implementations of an ISA have different latencies and hazards Chapter 4 The Processor 146

147 Does Multiple Issue Work? The BIG Picture Yes, but not as much as we d like Programs have real dependencies that limit ILP Some dependencies are hard to eliminate E.g., pointer aliasing Some parallelism is hard to expose Limited window size during instruction issue Memory delays and limited bandwidth Hard to keep pipelines full Speculation can help if done well Chapter 4 The Processor 147

148 Power Efficiency Complexity of dynamic scheduling and speculations requires power Multiple simpler cores may be better Microprocessor Year Clock Rate Pipeline Stages Issue width Out-of-order/ Speculation Cores Power i MHz 5 1 No 1 5W Pentium MHz 5 2 No 1 10W Pentium Pro MHz 10 3 Yes 1 29W P4 Willamette MHz 22 3 Yes 1 75W P4 Prescott MHz 31 3 Yes 1 103W Core MHz 14 4 Yes 2 75W UltraSparc III MHz 14 4 No 1 90W UltraSparc T MHz 6 1 No 8 70W Chapter 4 The Processor 148

149 The Opteron X4 Microarchitecture 72 physical registers 4.11 Real Stuff: The AMD Opteron X4 (Barcelona) Pipeline Chapter 4 The Processor 149

150 The Opteron X4 Pipeline Flow For integer operations FP is 5 stages longer Up to 106 RISC-ops in progress Bottlenecks Complex instructions with long dependencies Branch mispredictions Memory access delays Chapter 4 The Processor 150

151 Fallacies Pipelining is easy (!) The basic idea is easy The devil is in the details E.g., detecting data hazards Pipelining ideas can be implemented independent of technology So why haven t we always done pipelining? More transistors make more advanced techniques feasible Pipeline-related ISA design needs to take account of technology trends E.g., predicated instructions 4.13 Fallacies and Pitfalls Chapter 4 The Processor 151

152 Pitfalls Failure to consider instruction set design can adversely impact pipelining E.g., complex instruction sets (VAX, IA-32) Significant overhead to make pipelining work IA-32 micro-op approach E.g., complex addressing modes Register update side effects, memory indirection Chapter 4 The Processor 152

153 Concluding Remarks ISA influences design of datapath and control Datapath and control influence design of ISA Pipelining improves instruction throughput using temporal parallelism More instructions completed per second Latency for each instruction not reduced Hazards: structural, data, control Multiple issue and dynamic scheduling (ILP) Dependencies limit achievable parallelism Complexity leads to the power wall 4.14 Concluding Remarks Chapter 4 The Processor 153

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