Getting to Grips with the SystemVerilog Scheduler
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1 Getting to Grips with the SystemVerilog Scheduler Alan Fitch, Doulos 1
2 SystemVerilog Scheduler The Verilog Scheduler SystemVerilog 2005 SystemVerilog 2009/2012 Gotchas!... and Conclusions
3 Verilog Scheduler From previous time slot = Promotion #0 <= #T <= #T Future time slots $monitor To next time slot 3
4 SystemVerilog Scheduler Issues Safe (race-free) connections between test and design Integration of SystemVerilog Assertions (SVA) Allowing program blocks, clocking blocks, and modules to live in harmony 4
5 SystemVerilog Scheduler The Verilog Scheduler SystemVerilog 2005 SystemVerilog 2009/2012 Gotchas!... and Conclusions
6 SystemVerilog 2005 Assertions From previous time slot sample values for assertions = #N... #0 <= Assertion s clock event <= #N Creation of events Observed evaluate assertions if triggered Execution $strobe, $monitor To next time slot 6
7 SystemVerilog 2005 Testbench From previous time slot = #N... #0 <= <= #N write to design variables Creation of events Observed <= Execution #N... Re-active = Re-inactive #0 $strobe, $monitor write to testbench variables To next time slot 7
8 Program vs Module From previous time slot = #N... <= #N #0 <= MODULE and INTERFACE code schedules events here Observed <= #N... Re-active = Re-inactive #0 $strobe, $monitor To next time slot PROGRAM code schedules events here and here... 8
9 Clocking Block Outputs clocking event timeslot #2 later #2 Observe output #0 output #2 Observe Re-active Re-inactive TH.cb.D <=...; Re-active Re-inactive 9
10 Clocking Block Inputs earlier timeslots clocking event #165 #167 #170 input #1step DUT acts? Observe Observe Observe input #0 Re-active Re-active Re-active Re-inactive Re-inactive Re-inactive input #5 10
11 SystemVerilog Scheduler The Verilog Scheduler SystemVerilog 2005 SystemVerilog 2009/2012 Gotchas!... and Conclusions
12 Problems with SV 2005 Assigning in a clocking block (#0) or in a program executes in the region Which might trigger the observed region again Using program blocks without clocking blocks effectively samples at input #0 Potential race between clocking block and program block Procedural ##1 delay default clocking Clk); input #1step Q,D; endclocking; initial begin #1ns; ##1 $display(moncb.q,,moncb.d); end 12
13 SystemVerilog 2009 Scheduler From previous time slot #N... = Creation of events #0 <= Execution <= #N Observed Assertion action blocks #N... Re-active $strobe, $monitor Re-inactive #0 <= <= #N Re- write to output "clockvars" To next time slot 13
14 Procedural ## delays Procedural ## delay in was not well-defined In ##1 delay - if called not coincident with the clocking event of the clocking block, the calling process is delayed until the next clocking event ##0 If the clocking event has not occurred, suspend until is has; if it has, carry on without suspending See section of / initial begin #1ns; ##0 cb.d <= 1'b0; end initial begin #1ns; ##1 cb.d <= 1'b0; end 14
15 SystemVerilog Scheduler The Verilog Scheduler SystemVerilog 2005 SystemVerilog 2009/2012 Gotchas!... and Conclusions
16 Gotchas!... and Conclusions / is better! Things can still go wrong though... Known races between clocking blocks and programs, for instance the note on p305, input #0 or program without clocking block affected by non-zero DUT delays You may notice changes if you used ##0 or ##1 procedural delays in 2009/2012 Modules and Clocking blocks now "play nicely" Plan B - just use Modules and assign/read on clock falling edge?? 16
17 17
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