// Main testbench module. module testbench;
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1 `timescale 1ns / 1ps `define NULL 0 Company: ECE Spring 2015 Engineer: EO Student Assignment: Using the SystemVerilog system tasks for reading and writing to a file, develop a self-checking testbench for your Project 2 using the following test data: <X,Y> = <55,89>; <56,35>; <45,72>; <89,55>. (The full IEEE standard is available if you are on the UI network!) Use the testbench to perform a post-implementation timing simulation. Deliverables: PDF of testbench and any files (testvectors and results). No report or project archive! Basic Design: Read patterns from a pat file containing test vectors in the form of: <x> <y> <expected> <x> <y> <expected> Values are in decimal. Log output to file named output_test_results.log Main testbench module. module testbench; Signals to drive into the gcd_core logic clk; logic reset; logic load; logic [7:0] din; logic [7:0] gcd_result; logic done; Values read from file and iterated over logic [7:0] x; logic [7:0] y; logic [7:0] expected_result; -1-
2 Instantiate one of our GCD Core dudes. He will be fed the values and we will read his result after he says he is done. gcd_core uut (.clk(clk),.load(load),.rst(reset),.din(din),.gcd_rslt(gcd_result),.done(done) ); Variables to track files (fileno if you will?) integer file_input; integer file_output; Variables to track successful and unsuccessful cases. integer successful_cases = 0; integer failure_cases = 0; Simulation parameters parameter CLK_PRD = 100; parameter MAX_SIM_TIME = (CLK_PRD * 150); parameter HOLD_TIME = (CLK_PRD * 0.3); Fail Safe Stopper initial #(MAX_SIM_TIME) $finish; Establish our clock initial clk <= 0; forever #(CLK_PRD/2) clk = ~clk; Now we can get to the meat and potatoes! initial : maintest $display("starting Test Simulation"); Open the input file. Unfortunately I wasn't able to determine Vivado's -2-
3 search algorithm. I tried putting this file in the sim and the source directory but none worked. Guess I have to specify the full path. file_input = $fopen( "D:/input_test_vectors.pat", "r"); if (file_input == `NULL) $display("unable to open input file input_test_vectors.pat"); disable maintest; Now open our log output file file_output = $fopen("output_test_results.log", "w"); if (file_output == `NULL) $display("unable to open output file output_test_results.log"); disable maintest; We have the input and output open. Lets go! $fdisplay(file_output, "All test files open. Beginning run"); Process each line of the input file as long as the of file isn't found. Scan the x, y, and expected_result out of it and log that we are going to try those values. while(!$feof(file_input)) if ($fscanf(file_input, "%d %d %d", x, y, expected_result) == 3) $fdisplay(file_output, "BEGINNING TEST CASE: x:%d, y:%d, expected:%d", x, y, expected_result); Now simulate it by handing if off to the GCD clk); #HOLD_TIME; reset = 1; reset = 0; din = x; load = 1; din = y; load = 0; -3-
4 din = 8'bxxxxxxxx; I was worried this forever loop trick might break down and I would have to re-enable the forever_loop each time I disabled it but apparently the loop automatically re-enables after leaving it. : forever_loop clk); if (done) disable forever_loop; Tell the people what happened. $fdisplay(file_output, "GCD Completed successfully. Gave output of %d", gcd_result); See if it matched our expected value or not. if (expected_result == gcd_result) successful_cases++; $fdisplay(file_output, "SUCCESS: GCD successfully computed correct GCD value for %d and %d of %d", x, y, gcd_result); else failure_cases++; $fdisplay(file_output, "FAILURE: GCD incorrectly indicated GCD of %d and %d was %d", x, y, gcd_result); Put a format newline so the output file reads easier. $fdisplay(file_output, ""); Print out a summary $fdisplay(file_output, "Total Test Cases: %d", successful_cases + failure_cases); $fdisplay(file_output, "Total Successes : %d", successful_cases); $fdisplay(file_output, "Total Failures : %d", failure_cases); -4-
5 Close the open files. $fflush(file_output); $fclose(file_input); $fclose(file_output); $finish; module -5-
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