Problem Set 2 Solutions

Transcription

1 Problem Set 2 Solutions ECE 551: Digital System Design and Synthesis Fall A tabular description and a known good behavioral specification is given for a priority encoder. x indicates don t care in this table. a) Find a structural description for the priority encoder using only NAND (and NOT) gates. Your goal should be minimum multilevel logic, not speed. Equations C 2 I 7 + I 6 + I5 + I 4 = ( I 7 + I 6) + I5 + I 4 = I 7 + I6 + I5 I 4 I3 + I5 I 4 2 ( I 7 + I 6) + I5 I 4 ( I3 + I 2) C1 I = ( ( ) C0 I 7 + I 6 I5 + I 6 I 4 I3 + I6 I 4 I 2 I1 I 7 + I6 I5 + I 4 I3 + I 2 I1 Note: Equations are not in terms of NAND and NOT operations. The following schematics were used to convert to NAND and NOT gates. Schematic (AND-OR version) I7 I6 I5 I4 I3 I2 C2 C1 C0 I1 Schematic (NAND-NOT version) I7 I6 I5 I4 w1 w2 w4 I3 I2 w3 w9 w8 w7 w6 w5 I1 Note: Graphical conversion techniques were used to develop this schematic. C2 C1 C0 Structural Design module Priority_Encoder(I,C); input [7:1] I; output [2:0] C; 1 of 14

2 // 15 wires wire I7_bar, I6_bar, I5_bar, I4_bar, I3_bar, I2_bar; wire w1, w2, w3, w4, w5, w6, w7, w8, w9; // 18 gates not(i7_bar, I[7]); not(i6_bar, I[6]); not(i5_bar, I[5]); not(i4_bar, I[4]); not(i3_bar, I[3]); not(i2_bar, I[2]); nand(w1, I7_bar, I6_bar); // C[2] calculation not(w2, w1); nand(c[2], w2, I5_bar, I4_bar); nand(w3, I3_bar, I2_bar); // C[1] calculation nand(w4, I5_bar, I4_bar, w3); nand(c[1], w2, w4); nand(w5, I2_bar, I[1]); // C[0] calculation nand(w6, I3_bar, w5); nand(w7, I4_bar, w6); nand(w8, I5_bar, w7); nand(w9, I6_bar, w8); nand(c[0], I7_bar, w9); b) Design a parallel load, left shift register-based testbench for your design that 1) applies the following pair of sequences of vectors to both descriptions 2) compares the output of the known-good description to the output of your description and 3) gives out a 0 if the outputs match and a 1 if they do not for each line and for the entire test at the. Note that the first sequence of patterns is achieved by loading in the shift register and shifting until a 1 is in bit 7 filling the vacated position with 0. The second sequence of patterns is achieved by shifting one more time to getting all 0 s and then shifting filling the vacated position with 1. By having a flip-flop that is set when all 0 s occurs, the filling of the vacated position can be easily changed from 0 to 1. The simulation can be stopped after the 16 patterns by just picking the right run time. Testbench /** Filename: tpriority_encoder.v * * Written By: David Leonard * Last modified: 10/9/01 * Last modified: 10/16/01 CRK * Module implemented: Testbench for Priority Encoder * * Notes: Homework 2 Problem #1 * */ 2 of 14

3 module tpriority_encoder; wire unequal; // comparator output for comparison of C_S and C_B wire [2:0] C_S, // C of Structural Model C_B; // C of Behavorial Model reg [7:1] I; reg clock, inv, // if 1, fill shifter w/ 1s; otherwise, w/ 0s I0, // Place holder for LSB of shift result error; // Storage for accumulated unequal values initial I <= 7'b000_0001; clock <= 1'b0; inv <= 1'b0; I0 <= 1'b0; error <= 0; #70 inv <= 1'b1; always #5 clock = ~clock; always@(posedge clock) if (inv) else error <= error unequal; {I,I0} = {I,1'b1}<<1; {I,I0} = {I,1'b0}<<1; Priority_Encoder Structural(I,C_S); priority_encoder_b Behavorial(I,C_B); assign unequal = (C_S!== C_B); c) Compile and simulate to show that your design matches the known good design. Submit your code, your testbench code, and your simulation results (inputs and output) in list form with the meaningful lines highlighted. Input Vectors I[7:1] of 14

4 State Table I7 I6 I5 I4 I3 I2 I1 C2 C1 C0 1 X X X X X X X X X X X X X X X X X X X X X Known Good Design module priority_encoder_b (I,C); //THIS CODE IS AVAILABLE IN THE HOMEWORK FOLDER! input[7:1] I; output[2:0] C; reg[2:0] C; always@(i) if (I[7]) C = 3'b111; else if (I[6]) C = 3'b110; else if (I[5]) C = 3'b101; else if (I[4]) C = 3'b100; else if (I[3]) C = 3'b011; else if (I[2]) C = 3'b010; else if (I[1]) C = 3'b001; else C = 3'b000; List File ns /tpriority_encoder/i /tpriority_encoder/c_s /tpriority_encoder/c_b /tpriority_encoder/unequal /tpriority_encoder/error of 14

5 2. A negative edge-triggered D flip-flop with positive reset is described below. a) Find a UDP description for this flip-flop, which demonstrates a behavior identical to the given description. Note that negedge A represents the following transitions on A: a) (1x) (1z) - which in a UDP becomes (1x), and b) (10), (x0), (z0) - which in a UDP becomes (10) and (x0). This corresponds to n in the UDP notation. However, the behavior has been written to effectively exclude the case (1x). UDP Design primitive DFF(Q, clk, reset, D); input clk, reset, D; output Q; reg Q; initial Q = 1'bx; table // clk reset D : Q : Q+ p?? :? : -; (?0) 0 0 :? : 0; (?0) x 0 :? : 0; (?0) 0 1 :? : 1; (?0) x 1 :? : 1; (?0) 0 x :? : x; (?0) x x :? : x; (1x) 0? :? : -; (1x) x? :? : -; n 1? :? : 0;? (?1)? :? : 0;? (0x)? :? : -;? n? :? : -;?? * :? : -; table primitive b) Find a testbench that applies a set of vectors and compares outputs to show that the given description and your UDP have the same behavior for 1, 0, and x values and transitions applied. Limit your number of vectors to 20, but be sure to include cases with x s in the transitions on C. Testbench module tdff; wire unequal, U, B; reg clk, reset, D; initial clk <= 1'b1; D <= 1'b1; reset <= 1'b0; // Q+ = x #10 reset <= 1'b1; // Q+ = 0 #10 reset <= 1'b0; // Q+ = 0 5 of 14

6 #10 clk <= 1'b0; // Q+ = 1 #10 clk <= 1'b1; D <= 1'b0; reset <= 1'b0; // Q+ = 1 #10 clk <= 1'b0; // Q+ = 0 #10 clk <= 1'b1; D <= 1'bx; reset <= 1'bx; // Q+ = 0 #10 clk <= 1'b0; // Q+ = x #10 reset <= 1'b1; // Q+ = 0 #10 reset <= 1'bx; // Q+ = 0 #10 clk <= 1'b1; D <= 1'bx; reset <= 1'b0; // Q+ = 0 #10 clk <= 1'b0; // Q+ = x #10 clk <= 1'b1; D <= 1'b1; reset <= 1'b0; // Q+ = x #10 clk <= 1'b0; // Q+ = 1 #10 clk <= 1'b1; D <= 1'b0; reset <= 1'b0; // Q+ = 1 #10 clk <= 1'b0; // Q+ = 0 #10 clk <= 1'b1; D <= 1'b1; reset <= 1'bx; // Q+ = 0 #10 clk <= 1'b0; // Q+ = 1 #10 clk <= 1'b1; D <= 1'b0; reset <= 1'bx; // Q+ = 1 #10 clk <= 1'b0; // Q+ = 0 #10 $stop; DFF udp(u, clk, reset, D); neg_edge_ff behavioral(b, clk, reset, D); assign unequal = (U!== B); c) Compile and simulate to show that your design matches the known good design. Submit your code, your testbench code, and your simulation results (inputs and output) in list form with the meaningful lines highlighted. Known Good Design module neg_edge_ff (Q, clk, reset, D); input clk, reset, D; output Q; reg Q; always@(negedge clk or posedge reset) if (reset == 1) Q <= 1'b0; else if(clk == 0) Q <= D; List File ns unequal U B D clk reset 0 St0 StX StX St0 St0 St St0 St0 St St0 St1 St St0 St1 St St0 St0 St St0 St0 St0 1 x x 6 of 14

7 70 St0 StX StX 0 x x 80 St0 St0 St0 0 1 x 90 St0 St0 St0 0 x x 100 St0 St0 St0 1 0 x 110 St0 StX StX 0 0 x 120 St0 StX StX St0 St1 St St0 St1 St St0 St0 St St0 St0 St0 1 x St0 St1 St1 0 x St0 St1 St1 1 x St0 St0 St0 0 x 0 3. a) Add an enable EN_n (Active at 0) to a correct version of the quad 5-way multiplexer from Problem 10, Problem Set 1. Use a specify block to give the module the following delays: From EN_n to each Y output: 3 ns From each S input to each Y output: 4 ns From each bit of A,B,C,D, and E to the corresponding Y output bit: 2 ns Timing Design `timescale 1 ns / 100 ps module MUX5x4(Y, A, B, C, D, E, S, EN_n); input [3:0] A, B, C, D, E; input [2:0] S; input EN_n; output [3:0] Y; assign Y = {4{~EN_n}} & ({4{~S[2]&~S[1]&~S[0]}}&A {4{~S[2]&~S[1]&S[0]}}&B {4{~S[2]&S[1]&~S[0]}}&C {4{~S[2]&S[1]&S[0]}}&D {4{S[2]}}&E); specify (EN_n *> Y) = 3; (S *> Y) = 4; (A,B,C,D => Y) = 2; specify b) Compile and simulate for enough testbench transitions to show that part a gives the right delay. Use a timescale directive with 1 ns as the time unit and 100 ps as the simulation resolution. Submit your code, testbench code, and your simulation results (inputs and output) in list form with the meaningful lines highlighted. Testbench module tmux5x4; wire [3:0] Y; reg [3:0] A,B,C,D,E; 7 of 14

8 reg [2:0] S; reg EN_n; initial A <= 4'b0000; B <= 4'b0001; C <= 4'b0010; D <= 4'b0100; E <= 4'b1000; S <= 3'b000; EN_n <= 1'b0; #100 S <= 3'b001; #100 S <= 3'b010; #100 S <= 3'b011; #100 S <= 3'b100; #100 EN_n <= 1'b1; #100 S <= 3'b011; #100 S <= 3'b010; #100 S <= 3'b001; #100 S <= 3'b000; #100 $stop; MUX5x4 inst(y, A, B, C,D, E, S, EN_n); List File ns Y A B C D E S EN_n 0.0 xxxx Note: When EN_n = 1, output could also be zzzz as well as It deps on your interpretation of what an enable signal does when inactive. 8 of 14

9 4. A description for a finite state machine for timing simulation in Verilog is given. The description will be used to discuss the order in which the right hand sides RHS are evaluated and the left hand sides LHS are updated during Verilog simulation. Source timescale 1ns/1ns module fsm (clk, reset, a, b, c, state, next_state, 1 bx, by, bz, nbx, nby, nbz); 2 // THIS CODE IS AVAILABLE IN THE HOMEWORK FOLDER! 3 // This code is BAD FSM code! It is being used only to 4 // demonstrate Verilog simulation properties! 5 input clk, reset, a, b, c; 6 output bx, by, bz, nbx, nby, nbz; 7 output[2:0] next_state, state; 8 reg [2:0] next_state, state; 9 reg bx, by, bz, nbx, nby, nbz; 10 parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011, 11 S4 = 3'b100, S5 = 3'b101, S6 = 3'b110, S7 =3'b111; 12 // The State Register 13 always@(posedge clk or posedge reset) if (reset == 1) state <= S0; 16 else state <= next_state; // The Next State Logic 19 always@ (a or b or c or state) next_state = S0; 22 if (a == 1) next_state = S1; 23 else next_state = S2; 24 # 2 if (b == 0) next_state = S3; 25 else next_state = S4; 26 if (state == S3 && c == 0) next_state = #3 S5; 27 else next_state = #4 S6; 28 if (state == S4 && c == 0) next_state = #3 S7; 29 else next_state = S0; // The Output Logic (blocking) 32 always@ (a or b or c or state) bx = 1'b0; 35 #2 by = 1; 36 bz = #3 0; 37 if (state == S1) bx = 1; 38 if (state == S2) by = 0; 39 if (state == S3 && a == 1) bx = #2 1; 40 if (state == S4) by = #2 0; 41 if (state == S5) bx = 1; 42 if (state == S7) bz = 1; // The Output Logic (nonblocking) 45 always@ (a or b or c or state) nbx <= 1'b0; 48 9 of 14

10 #2 nby <= 1; 49 nbz <= #3 0; 50 if (state == S1) nbx <= 1; 51 if (state == S2) nby <= 0; 52 if (state == S3 && a == 1) nbx <= #2 1; 53 if (state == S4) nby <= #2 0; 54 if (state == S5) nbx <= 1; 55 if (state == S7) nbz <= 1; For each of the present value sets listed in the table below and a single positive clock transition: a) Describe the order of evaluation(e) of the RHS and of update(u) of the LHS for each assignment statement executed. You are to represent the ordering graphically including: 1) timestep of evaluation and update, 2) ordering of statement evaluation and statement update whenever the statement execution must be ordered and 3) timestep positioning of statements or ordered statement sets that are not ordered with respect to each other. Assignment statements are to be identified by the line number on the right of the Verilog code. Note that this applies only to assignment statements, not if else, etc. The latter, however, may affect which if the assignment statements are executed. Case #1 at t =20 a b c = 000 state = S0 next-state = S2 Positive Edge at t = 20 t = 20 E17, U17 E22, U22, E24, U24 E35, U35 E48, U48 t = 22 E25, U25, E28 E36, U36, E37 E49, E50, U49 t = 25 U37 U50 t = 26 U28, E30, U30 Case #2 at t =20 a b c = 000 state = S7 next-state = S2 Positive Edge at t = 20 t = 20 E17, U17 E22, U22, E24, U24 E35, U35 E48, U48 t = 22 E25, U25, E28 E36, U36, E37 10 of 14

11 t = 25 t = 26 E49, E50, E56, U49, U56 U37, E43, U43 U50 U28, E30, U30 t = 30 t = 32 t = 35 t = 36 E22, U22, E23, U23 E35, U35 E48, U48 E26, U26, E28 E36, U36, E37 E49, E50, E56, U49, U56 U37, E43, U43 U50 U28, E30, U30 Note: Both cases are assuming that the FSM was reset from t = 2 to 4 and that the states given were changed to those shown. b) In the empty locations in the table, give the resulting progression of output values over time for state, next_state, and the outputs until all activity due to a given positive clock edge has died out. Assume that the inputs a, b, c have not changed since early in the clock period prior to the positive clock edge. The clock period is 20 ns. Note that there are input changes that occur a portion of the way through the clock period. Time state a b c next_state bx by bz nbx nby nbz 0->4 S S3 0 1 x 0 1 x 20 (PE) S S S S S S S S S S >4 S S3 0 1 x 0 1 x 20 (PE) S S S S S S S S S S S S S S S S of 14

12 c) Show that the values you listed occur at the time you indicate by simulating fsm.v to produce outputs you can compare manually to those given in the table. Perform three simulations, using a testbench to apply the values sets in the table to a copy of the fsm module, which has been modified to initialize the state value at reset to that in the value set. It is suggested the reset go to 1 at time 2, back to 0 at time 4 with the clock edge at time 20. The events of interest occur in response to the positive clock edge just after the reset activation is complete. Submit your testbenches and your output (either table or list) clearly annotated to show that it matches your predicted table entries. Source #1 Same as Source above, but line 16 is if (reset == 1) state <= S3; Testbench #1 `timescale 1 ns/ 1 ns module tfsm; wire [2:0] next_state, state; wire bx, by, bz, nbx, nby, nbz; reg clk, reset, a, b, c; initial a <= 1'b0; b <= 1'b0; c <= 1'b0; clk <= 1'b0; reset <= 1'b0; #2 reset <= 1'b1; #2 reset <= 1'b0; #16 clk <= 1'b1; #10 clk <= 1'b0; #10 $stop; FSM inst(clk, reset, a, b, c, state, next_state, bx, by, bz, nbx, nby, nbz); Listing #1 ns next_state bx by bz nby clk a c state nbx nbz b reset xxx St0 StX StX St0 StX StX St0 St1 StX St0 St1 StX St0 St1 StX St0 St1 StX St0 St1 St0 St0 St1 St St0 St1 St0 St0 St1 St St0 St1 St0 St0 St1 St St0 St1 St0 St0 St1 St St0 St1 St0 St0 St1 St St0 St1 St0 St0 St1 St of 14

13 Source #2 Same as Source above, but line 16 is if (reset == 1) state <= S4; Testbench #2 `timescale 1 ns/ 1 ns module tfsm; wire [2:0] next_state, state; wire bx, by, bz, nbx, nby, nbz; reg clk, reset, a, b, c; initial a <= 1'b0; b <= 1'b0; c <= 1'b0; clk <= 1'b0; reset <= 1'b0; #2 reset <= 1'b1; #2 reset <= 1'b0; #16 clk <= 1'b1; #10 clk <= 1'b0; a <= 1'b1; b <= 1'b1; c <= 1'b0; #10 $stop; FSM inst(clk, reset, a, b, c, state, next_state, bx, by, bz, nbx, nby, nbz); Listing #2 ns next_state bx by bz nby clk a c state nbx nbz b reset xxx St0 StX StX St0 StX StX St0 St1 StX St0 St1 StX St0 St1 StX St0 St1 StX St0 St1 St0 St0 St1 St St0 St1 St0 St0 St0 St St0 St0 St0 St0 St0 St St0 St0 St0 St0 St0 St St0 St0 St0 St0 St0 St St0 St1 St0 St0 St1 St St0 St1 St1 St0 St1 St St0 St1 St1 St0 St1 St St0 St1 St1 St0 St1 St St0 St1 St1 St0 St1 St St0 St1 St1 St0 St1 St St0 St1 St1 St0 St1 St of 14

14 5. Write a procedural description for the given combinational circuit using a sequence of blocking procedural statements. Compile your result to get rid of at least some of the syntax errors. Procedural Design module UF(F, G, A, B, C, D); input A, B, C, D; output F, G; reg F, G; reg T1, T2, T3, T4, T5; // wires always@(a or B or C or D) T1 = ~(A&C); T2 = ~(A&B&D); T3 = ~(B&C&D); F = ~(A&T1&T2); T4 = ~(B&T2&T3); T5 = ~(T1&C&T3); G = ~(F&T4&T5); Note: Procedural continuous assignments are not blocking procedural statements. 14 of 14