List of Examples List of Figures List of Tables. Acknowledgments 1. VERIFICATION GUIDELINES 1

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1 Contents List of Examples List of Figures List of Tables Preface Acknowledgments xiii xxvii xxix xxxi xxxvii 1. VERIFICATION GUIDELINES The Verification Process The Verification Methodology Manual Basic Testbench Functionality Directed Testing Methodology Basics Constrained-Random Stimulus What Should You Randomize? Functional Coverage Testbench Components Layered Testbench Building a Layered Testbench Simulation Environment Phases Maximum Code Reuse Testbench Performance Conclusion Exercises DATA TYPES Built-In Data Types Fixed-Size Arrays Dynamic Arrays Queues 38

2 viii SystemVerilog for Verification 2.5 Associative Arrays Array Methods Choosing a Storage Type Creating New Types with typedef Creating User-Defined Structures Packages Type conversion Streaming operators Enumerated Types Constants Strings Expression Width Conclusion Exercises PROCEDURAL STATEMENTS AND ROUTINES Procedural Statements Tasks, Functions, and Void Functions Task and Function Overview Routine Arguments Returning from a Routine Local Data Storage Time Values Conclusion Exercises CONNECTING THE TESTBENCH AND DESIGN Separating the Testbench and Design The Interface Construct Stimulus Timing Interface Driving and Sampling Program block considerations Connecting It All Together Top-Level Scope Program Module Interactions SystemVerilog Assertions The Four-Port ATM Router The ref port direction Conclusion Exercises 130

3 Contents ix 5. BASIC OOP Introduction Think of Nouns, not Verbs Your First Class Where to Define a Class OOP Terminology Creating New Objects Object Deallocation Using Objects Class Methods Defining Methods Outside of the Class Static Variables vs. Global Variables Scoping Rules Using One Class Inside Another Understanding Dynamic Objects Copying Objects Public vs. Local Straying Off Course Building a Testbench Conclusion Exercises RANDOMIZATION Introduction What to Randomize Randomization in SystemVerilog Constraint Details Solution Probabilities Controlling Multiple Constraint Blocks Valid Constraints In-line Constraints The pre_randomize and post_randomize Functions Random Number Functions Constraints Tips and Techniques Common Randomization Problems Iterative and Array Constraints Atomic Stimulus Generation vs. Scenario Generation Random Control Random Number Generators Random Device Configuration Conclusion Exercises 226

4 x SystemVerilog for Verification 7. THREADS AND INTERPROCESS COMMUNICATION Working with Threads Disabling Threads Interprocess Communication Events Semaphores Mailboxes Building a Testbench with Threads and IPC Conclusion Exercises ADVANCED OOP AND TESTBENCH GUIDELINES Introduction to Inheritance Blueprint Pattern Downcasting and Virtual Methods Composition, Inheritance, and Alternatives Copying an Object Abstract Classes and Pure Virtual Methods Callbacks Parameterized Classes Static and Singleton Classes Creating a Test Registry Conclusion Exercises FUNCTIONAL COVERAGE Coverage Types Functional Coverage Strategies Simple Functional Coverage Example Anatomy of a Cover Group Triggering a Cover Group Data Sampling Cross Coverage Generic Cover Groups Coverage Options Analyzing Coverage Data Measuring Coverage Statistics During Simulation Conclusion Exercises ADVANCED INTERFACES Virtual Interfaces with the ATM Router Connecting to Multiple Design Configurations 374

5 Contents xi 10.3 Parameterized Interfaces and Virtual Interfaces Procedural Code in an Interface Conclusion Exercises A COMPLETE SYSTEMVERILOG TESTBENCH Design Blocks Testbench Blocks Alternate Tests Conclusion Exercises INTERFACING WITH C / C Passing Simple Values Connecting to a Simple C Routine Connecting to C Simple Array Sharing Open arrays Sharing Composite Types Pure and Context Imported Methods Communicating from C to SystemVerilog Connecting Other Languages Conclusion Exercises 457 References 459 Index 461

6 xii SystemVerilog for Verification