Digital System Design with SystemVerilog

Transcription

1 Digital System Design with SystemVerilog Mark Zwolinski AAddison-Wesley Upper Saddle River, NJ Boston Indianapolis San Francisco New York Toronto Montreal London Munich Paris Madrid Capetown Sydney Tokyo Singapore Mexico City

2 Contents List of Figures xiii List of Tables xix Preface xxi Acknowledgments xxvii About the Author xxix 1. Introduction Modern Digital Design Designing with Hardware Description Languages Design Automation What is SystemVerilog? WhatisVHDL? Simulation Synthesis Reusability Verification Design Flow CMOS Technology Logic Gates ASICs and FPGAs Programmable Logic Electrical Properties Noise Margins Fan-Out 20 Summary 22 Further Reading 22 Exercises 23

3 2. Combinational Logic Design Boolean Algebra Values Operators Truth Tables Rules of Boolean Algebra De Morgan's Law Shannon's Expansion Theorem Logic Gates Combinational Logic Design Logic Minimization Karnaugh Maps Timing Number Codes Integers Fixed Point Numbers Floating Point Numbers Alphanumeric Characters Gray Codes Parity Bits 43 Summary 43 Further Reading 44 Exercises Combinational Logic Using SystemVerilog Gate Models 3.1 Modules and Files Identifiers, Spaces, and Comments Basic Gate Models A Simple Netlist Logic Values Continuous Assignments System Verilog Operators Delays Parameters Testbenches 56 Summary 58 Further Reading 58 Exercises 58

4 Contents 4. Combinational Building Blocks Multiplexers to 1 Multiplexer to 1 Multiplexer Decoders to 4 Decoder Parameterizable Decoder Seven-Segment Decoder Priority Encoder Don't Cares and Uniqueness Adders Functional Model Ripple Adder Tasks Parity Checker Three-State Buffers Multi-Valued Logic Testbenches for Combinational Blocks 74 Summary 76 Further Reading 76 Exercises SystemVerilog Models of Sequential Logic Blocks Latches SR Latch D Latch Flip-Flops Edge-Triggered D Flip-Flop Asynchronous Set and Reset Synchronous Set and Reset and Clock Enable 5.3 JK and T Flip-Flops Registers and Shift Registers Multiple Bit Register Shift Registers Counters Binary Counter Johnson Counter Linear Feedback Shift Register 95

5 viii Contents 5.6 Memory ROM SRAM Synchronous RAM Sequential Multiplier Testbenches for Sequential Building Blocks Clock Generation Reset and Other Deterministic Signals Checking Responses 104 Summary 106 Further Reading 106 Exercises Synchronous Sequential Design Synchronous Sequential Systems Models of Synchronous Sequential Systems Moore and Mealy Machines State Registers Design of a Three-Bit Counter Algorithmic State Machines Synthesis from ASM Charts Hardware Implementation State Assignment State Minimization State Machines in System Verilog A First Example A Sequential Parity Detector Vending Machine Storing Data Testbenches for State Machines 137 Summary 138 Further Reading 138 Exercises Complex Sequential Systems Linked State Machines Datapath/Controller Partitioning Instructions A Simple Microprocessor System Verilog Model of a Simple Microprocessor 156

6 Contents ix Summary 165 Further Reading 165 Exercises Writing Testbenches Basic Testbenches Clock Generation Reset and Other Deterministic Signals Monitoring Responses Dumping Responses Test Vectors from a File Testbench Structure Programs Constrained Random Stimulus Generation Object-Oriented Programming Randomization Assertion-Based Verification 178 Summary 182 Further Reading 183 Exercises System Verilog Simulation Event-Driven Simulation System Verilog Simulation Races Avoiding Races Delay Models Simulator Tools 195 Summary 196 Further Reading 196 Exercises System Verilog Synthesis RTL Synthesis Non-Synthesizable System Verilog Inferred Flip-Flops and Latches Combinational Logic Summary of RTL Synthesis Rules Constraints Attributes 211

7 Area and Structural Constraints full_case and parallel_case Attributes 10.3 Synthesis for FPGAs Behavioral Synthesis Verifying Synthesis Results Timing Simulation 226 Summary 228 Further Reading 228 Exercises Testing Digital Systems The Need for Testing Fault Models Single-Stuck Fault Model PLA Faults Fault-Oriented Test Pattern Generation Sensitive Path Algorithm Undetectable Faults The D Algorithm PODEM Fault Collapsing Fault Simulation Parallel Fault Simulation Concurrent Fault Simulation 244 Summary 246 Further Reading 246 Exercises Design for Testability Ad hoc Testability Improvements Structured Design for Test Built-in Self-Test Example Built-in Logic Block Observation (BILBO) 12.4 Boundary Scan (IEEE ) 264 Summary 272 Further Reading 272 Exercises 272

8 Contents xi 13. Asynchronous Sequential Design Asynchronous Circuits Analysis of Asynchronous Circuits Informal Analysis Formal Analysis Design of Asynchronous Circuits Asynchronous State Machines Setup and Hold Times and Metastability The Fundamental Mode Restriction and Synchronous Circuits SystemVerilog Modeling of Setup and Hold Time Violations Metastability 300 Summary 302 Further Reading 302 Exercises Interfacing with the Analog World Digital-to-Analog Converters Analog-to-Digital Converters Verilog-AMS Verilog-AMS Fundamentals Contribution Statements Mixed-Signal Modeling Phased-Locked Loops Verilog-AMS Simulators 323 Summary 323 Further Reading 324 Exercises 324 A. SystemVerilog and Verilog 325 A.1 Standards 325 A.2 SystemVerilog and Verilog Differences 326 Answers to Selected Exercises 331 Bibliography 347 Index 349