Lab 6 Using PicoBlaze. Fast Sorting.

Transcription

1 Lab 6 Using PicoBlaze. Fast Sorting. Design, implement, and verify experimentally a circuit shown in the block diagram below, composed of the following major components: PicoBlaze-6 microcontroller with dedicated Instruction RAM Single-port 256x8 Data RAM (out of which we use only 255 locations) 8-bit Programmable Pseudorandom Number Generator (PRNG) with hardwired control unit and internal registers PRNG_STATUS and PRNG_CTRL Input Interface with the internal registers BUTTON and SWITCH Cycle Counter and Output Interface with the internal registers SSD3-SSD0 and CCOUNT, and the input connected to the switch S7 Address Decoder During configuration, 256x8 RAM should be initialized to values {"00", "01",..., "FE", FF"}, i.e., the value at each location should be equal to the address of that location.

2 The clk signal is not shown in the diagram, but is assumed to be connected to each synchronous component. The PicoBlaze should be able to access Data RAM and internal registers of Input Interface, Cycle Counter and Output Interface, and PRNG using Memory Map shown in the diagram below: The Memory Map consists of two banks of memory: Bank 0, covering addresses 000 to 0FF, includes 255 locations of Data RAM and the MEM_BANK register. Bank 1, for memory mapped I/O, covers addresses 100 to 1FF, and includes 11 registers: BUTTON, SSD3-SSD0, LED, PRNG_STATUS, PRNG_CTRL, SWITCH, CCOUNT, and MEM_BANK.

3 The register MEM_BANK is visible under two memory addresses 0FF and 1FF (writing to both of these addresses changes the same register). Writing 0 to the least significant bit of MEM_BANK, changes the bank to Bank 0, and sets the most significant bit of the address A[8] to 0, until the next write to MEM_BANK. Writing 1 to the least significant bit of MEM_BANK, changes the bank to Bank 1, and sets the most significant bit of the address A[8] to 1, until the next write to MEM_BANK. Input Interface contains the register BUTTON. The five least significant bits of this register correspond to the recent press of the button Select, Right, Left, Up, and Down, respectively. The most significant bit of the BUTTON register, A, is equal to 1 if any button was recently pressed. All bits are cleared by reading the register BUTTON. PicoBlaze becomes aware of any button being pressed using polling or interrupts (20% bonus points for using interrupts; see Task 6). The input interface also contains the register SWITCH, which contains values of 8 switches of the board.

4 PRNG has two modes of operation: Idle and Active. In the default Idle mode, rinit =0, R_wen = 0, RA = 00, and RD = the current state of PRNG. Writing 1 to the bit I of PRNG_CTRL changes the mode of PRNG to Active, and clears the bit D of PRNG_STATUS. In the Active mode, rinit =1, R_wen = 1, RA changes between 00 and FE, and RD is equal to a new 8-bit random number every clock cycle. After 255 clock cycles, the bit D (Done) of PRNG_STATUS is set to 1, and bit I of PRNG_CTRL is cleared. Reading PRNG_STATUS clears bit D. The pseudorandom number generator should be based on the Linear Congruential Generator (LCG), as shown in the diagram below. An LCG generates a sequence of pseudo-random numbers according to the following recurrence congruence. The LCG will have an 8-bit state (m = 2 8 ). R n+1 = a * R n + c (mod m) where R n is the sequence of pseudorandom values, a is the multiplier, c is the increment and m is the modulus. R 0 is the initial seed value. Please assume the following default values of parameters a, c, and R 0 : a= 0x11, c= 0x9D, R 0 = 0xD7. Additionally, assume that * represents an unsigned multiplication. a 8 R c = 8-bit register with a set signal to to R 0 after soft reset The LCG generates one output per one clock cycle. In our circuit, PRNG is used to initialize Data RAM. Each time an initialization is performed, the PRNG should start from a different state, which is a last state reached during the previous initialization (please note that the "soft" reset does not change the memory contents).

5 The program of PicoBlaze should support the following five major modes of operation: Browsing mode (LED0=1) Initialization mode (LED1=1) Sorting mode (LED2=1) Cycle Count Display mode (LED3=1). Switch S2 should be used as soft reset. "Soft" reset should have the following effect: current mode should be set to the Browsing mode current value of the memory address should be set to 0, and this address and the data at this address should be displayed using four seven segment displays. Pseudorandom Number Generator should be initialized to R 0. The modes are defined below, and their implementation constitutes subsequent tasks. Task 1 Browsing Mode In the Browsing Mode, the circuit should display Current Address (using Seven Segment Displays 3 and 2) Value in Data RAM at position given by the Current Address (using Seven Segment Displays 1 and 0). Button Up should increment the Current Address in the wrap-around fashion ("FE" followed by "00"). Button Down should decrement the Current Address in the wrap-around fashion ("00" followed by "FE"). Task 2 Initialization Mode In this mode, each time Button Left is pressed, the entire memory is initialized with 255 pseudorandom values generated by the 8-bit Pseudorandom Number Generator. The initialization should not affect the value of the Current Address. After the initialization is complete, you should return to the Browsing Mode. Task 3 Sorting Mode Pressing Button Select should initiate sorting. The processed numbers should be treated as signed numbers, and should be sorted in the descending order. During sorting ---- should be displayed on the seven segment displays. Task 4 Cycle Count Display Mode After sorting the total number of clock cycles used for sorting should be displayed on the seven segment displays. The position of switch S7 should indicate whether the least significant 16 bits of the Cycle Counter (for S7=0), or the most significant 16 bits of the Cycle Counter (for S7=1) should be displayed. Pressing any button (other than Select) after sorting, should bring the circuit back to the browsing mode.

6 Task 5 Interrupts (Bonus) Modify your circuit in such a way that it generates an interrupt each time any button is pressed. Modify your assembly language program accordingly, by replacing polling by an interrupt serving routine Consider using Register Bank switching in your interrupt service routine (if appropriate). Contest for the Fastest Implementation of Sorting Bonus points will be awarded to students who perform sorting (correctly) using the smallest number of clock cycles. Possible optimizations include (but are not limited to): Faster sorting algorithms in software Efficient assembly language implementation Hardware Control Unit (in place of PicoBlaze) Faster sorting algorithms in hardware Efficient hardware implementation Perform the following tasks to verify the correctness of your designs: 1. Debug your assembly language program using programming environment introduced during the lab. 2. Perform functional simulation. 3. Synthesize your code. 4. Prepare the UCF (User Constraints File) specifying pin allocations. 5. Implement your code using an appropriate UCF file and chip specification. 6. Check thoroughly implementation reports. Pay attention to pin allocations. Find out what is the maximum clock frequency your circuit can operate at. 7. Download the bitstream to the FPGA board. 8. Verify experimentally the correct operation of your circuit. Include in the lab report: 1. A detailed block diagram of the Datapath of your circuit. 2. Assembly language source codes. 3. VHDL code of your circuit and all testbenches used to verify this circuit. 4. Your UCF file for FPGA. 5. Simulation waveforms from the functional simulations, proving the correct operation of your circuit. 6. A short report listing all tasks completed successfully and any problems encountered. For the most advanced task you implemented, determine the following parameters of the entire circuit: number of clock cycles used for sorting 255 numbers obtained using the first initialization after reset maximum clock frequency critical path resource utilization.

7 Important Dates Hands-on Sessions and Introductions to the Experiment Demonstration and Deliverables Due for Schedule A Demonstration and Deliverables Due for Schedule B Monday Section Tuesday Section Wednesday Section 04/18/ /19/ /20/ /02/ /03/ /04/ /09/ /10/ /11/2016