Midterm Exam ECE 448 Spring 2014 Monday, March 3 (15 points)

Transcription

1 ECE8 Midterm Midterm Exam ECE 8 Spring 2 Monday, March 3 (5 points) Instructions: Zip all your delierables into an archie <last_name>.zip and submit it through lackboard no later than Monday, March 3, :5 PM EDT.

2 ECE8 Midterm Lab Midterm Exam The circuit described below performs the multiplication operation in the binary format, and then expresses the result in the CD format. The design accepts an 8-bit unsigned multiplicand and a -bit unsigned multiplier. It uces a -bit result in CD format. Signal "start" is used to initiate the operation. The circuit is specified below using its: Ø Interface Ø Table of input/output ports Ø lock diagram Ø Test ectors Ø Timing waeforms from functional simulation Top-leel iew of Multiplier: ssume the following top-leel iew to your circuit. clk 8 top start done 2

3 ECE8 Midterm ssume the following diision of your circuit into the Datapath and Controller. 8 clk start Datapath load_a load_b en_a en_b en_i sel zi Controller done Table of input/output ports: Port Mode width Function clk IN System clock IN synchronous system reset IN 8 Multiplicand IN Multiplier start IN signal to initiate multiplication operation OUT Result of the multiplication in CD format done OUT signal to show the end of operation 3

4 ECE8 Midterm lock diagram: 8 MULT sel en_a load_a sel sel clk en ld clk shift_reg_ sin en_b load_b en ld shift_reg_ sin = 999 load_b en_i ld counter en = clk _reg _reg() _reg zi _reg(3..) > c cin sum DD cout _reg(7..) > c cin sum DD2 cout _reg(..8) > c2 cin sum DD3 cout

5 ECE8 Midterm SM Chart: S start S en_a, load_a, en_b, load_b, en_i, sel = S done S2 en_a en_b en_i S3 en_a, load_a sel = zi Test ectors: Inputs: = x"e" = 78 (in decimal) = x"9" = 9 (in decimal) Output: = x"2e" = 72 (in decimal) = 5

6 ECE8 Midterm Inputs: = x"" = 7 (in decimal) = x"9" = 9 (in decimal) Output: = undefined (out of range) = Design Requirements: The combinational portion of the circuit should be described using the dataflow VHDL code, and the sequential portion of the circuit should be described using the synthesizable behaioral code. Your code should infer a circuit that requires a minimum amount of FPG resources. The target clock frequency should be MHz. Tasks: Perform the following tasks:. Write a synthesizable VHDL code representing the multiplication circuit 2. Write a testbench erifying the operation of your circuit. 3. Perform functional simulation of your circuit and use it to debug your VHDL code. Take a print out of the waeform showing the entire operation using default PDF conersion tool installed in the lab (Use multiple page option in order to display necessary information on multiple pages, if required).. Synthesize your circuit. 5. Implement your circuit using a. FPG family: Spartan 6 b. Deice: xc6slx6-3csg32 c. Speed Grade: Run the static timing analysis of your circuit. 7. ased on the circuit block diagram and the report from the static timing analysis, determine the most critical path in your circuit and the circuit maximum clock frequency. 8. ased on the implementation reports, determine the number of CL slices, LUTs, flip-flops, and pins used by the circuit. 9. Perform the timing simulation of your circuit at the maximum clock frequency returned by the static timing analysis. Take a printout of the waeform showing the entire operation using default PDF conersion tool installed in the lab (Use multiple page option in order to display necessary information on multiple pages, if required). 6

7 ECE8 Midterm Delierables:. VHDL code of your entire circuit fulfilling the requirements specified in the Design Requirements section aboe. 2. VHDL code of your testbench. 3. Timing waeforms from the functional and timing simulations demonstrating the correct operation of your circuit.. Description of the critical path in your circuit 5. FPG resource utilization (as defined in Task 8 aboe). 6. Minimum clock period and maximum clock frequency of your circuit. 7