EE431 April 6, 2009 Midterm Material on Assignments 6 to 10

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1 EE431 April 6, 2009 midterm 1 EE431 April 6, 2009 Midterm Material on Assignments 6 to 10 Date: Monday April 6, 2009 Time = 2 hours Text Books, Notes and Computer Files Only NO CELL PHONES or LAPTOPS Preamble This exam is based on a verilog module called exam test bench It is provided for you on the I drive. Instructions on how to retrieve it are given later. The port list (Verilog 2001 extension format) for this module is given below. module exam_test_bench_2009 ( input clk, clear, input [7:0] seed, input [7:0] exam_number, output reg [7:0] stimulus, output reg [7:0] response, output reg counter_full_bar, output reg [15:0] accumulator_output ); // verilog 2001 extension It has four inputs and four outputs. In this exam you will be simulating the circuit built from prototype exam test bench You will have to create a vector waveform file (i.e. a.vwf file) and make waveforms for the four inputs. Input seed will be an 8 bit constant given in the answer sheet. The input exam number will also be an 8-bit constant. It will be either be set to 8 d00 or set to the exam number (e.g. if your exam is exam number 3 then exam number is set to 8 d3). Inputs clear and clk are waveforms that will be described in the questions. Output stimulus and response are provided to help the you with debugging. You may or may not want to use them. Their values are not reported in this exam. You are to report the value of accumulator output at the time when the output called counter full bar is low. Questions (5) 1. Make a folder named Apr midterm. Copy the verilog file exam test bench 2009.v, from directory I drive (I:) classes EE to the new folder. Copy the verilog file student circuit.v, from directory I drive (I:) classes EE431 to the new folder.

2 EE431 April 6, 2009 midterm 2 exam_number 8 clk scrambler_input 8 clk address ROM 1 8 bits/word 256 words data_out clk address ROM 2 8 bits/word 256 words data_out exam 0 not exam 0 8 H0 A B A==B scrambler_output Figure 1: The scrambler to be designed by the student Copy the hex file ROM 1.hex from directory I drive (I:) classes EE431 to the new folder. Copy the hex file Q3 and Q4.hex from directory I drive (I:) classes EE431 to the new folder. Make a Quartus II project called exam test bench 2009 and make Apr midterm the working directory. Make module exam test bench 2009 the top entity. Add the files you copied to the project. Be sure to choose the Cyclone II FPGA family. Design module student scrambler as per Figure 1. Both of the read only memories are synchronous with no registers on the output. Rom 1 is to be initialized with the hex file that is provided, i.e. ROM 1.hex. The hex file to be used for ROM 2 is obtained by modifying the hex file ROM 1.hex as per the instructions on the back of cover page of the exam. There is an instantiation of student scrambler in the top entity, which is exam test bench This intantatiation has to be modified. The student scrambler designed in this question has no clear input so the connection in the connection list that involves clear must be removed.

3 EE431 April 6, 2009 midterm 3 (a) Compile exam test bench 2009.v. NOTE: The compiler will issue some warnings. They should be the usual warnings of undefined clock, capacitance not assigned to pins, etc. Read them to make sure they can be safely ignored. (b) Open a waveform/vector file. (c) Make the simulation time 300 µs. (d) Import all the input and output pins into the.vwf file. (e) Make the clock, which is clk, a square clock with period 1 µs. The clock should start low and make a transition to high at 0.5 µs. (f) Make input clear a pulse that is high from 0 to 5.2 ± 0.1 µs and low for the remainder of the simulation. (g) Make input seed, the constant 8 HFF for the duration of the simulation. (h) Make input exam number the constant 8 d0 for the duration of the simulation. (i) Perform a simulation. (j) Observe accumulator output when counter full bar is a steady 1 b0. If your circuit is working properly the output should be as indicated on the answer sheet. (k) Change the input exam number to a constant equal your exam number. If your exam number is 3, then make the constant 8 d3. Do not change the input seed, it should be the constant 8 HFF. Simulate the circuit again and then observe accumulator output when counter full bar is 1 b0. If your circuit is working properly the output should be as indicated on the answer sheet. (l) Change the seed. Make it the constant 8 HAA for the duration simulation. (m) Make the exam number 8 H00 for the duration of the simulation. Then simulate and report the value of accumulator output during the time counter full bar is 1 b0. (n) Make the exam number the constant equal to your exam number (obviously for the duration of the simulation). Then simulate and report the value of accumulator output during the time counter full bar is 1 b0. (5) 2. This question uses the same quartus project as Question 1. Copy all your microprocessor verilog files to the project folder and add them to the quartus project.

4 EE431 April 6, 2009 midterm 4 In exam test bench 2009 there is an instantiation of student circuit. Relace it with an instantiation of your microprocessor. To be very specific, delete the instantiation of student circuit in module exam test bench 2009 and then instatiate your miroprocessor. Mimic the instantiation of the instructor s microprocessor that is given below. EE431_microprocessor (.clk(clk),.reset(clear),.i_pins(stimulus[3:0]),.o_reg(cct_output[3:0]) ); Modify the instantiation of student scrambler as per the instantiation below. student_scrambler scmblr_1(.clk(clk),.exam_number(exam_number),.scrambler_input({stimulus[7:4],cct_output[3:0]}),.scrambler_output(response) ); Then hand assemble a three line program for your microprocessor (Do not use the EE431 assembler as it requires web access.). The three line program is to occupy program memory locations 8 H00, 8 H01 and 8 H02. The program is to read i pins with the first instruction, put the contents of i pins in o reg on the second instruction and execute a jump to location 8 H00 on the third instruction. Make the hex file for the program memory ROM. Compile exam test bench 2009 and simulate making the seed and exam number as required to fill out the answer sheet. (5) 3. For this question use the same Quartus project as in Questions 1 and 2. For this question you are to use hex file Q3 and Q4.hex to initialize your program memory. You should have already copied this file to your project folder. It you haven t, the file can be found on the I drive. Modify your microprocessor to include a 4-bit counter called timer. The rules of operation are simple. timer decrements by 4 b1 on each rising edge of clk except on those edges when sync reset is active. On the rising edges of clk when sync reset is active, timer is reset to 4 b0. It is entirely up to you where you make timer. Of course it must be part of one of the modules in your microprocessor project. It will be used in the question that follows so you should read that question before deciding where to build this

5 EE431 April 6, 2009 midterm 5 counter called timer. After timer is built make it an output port in your microprocessor and change the instantiation of your microprocessor in exam test bench 2009 to mimic the instantiation of the instructor s modified microprocessor that is given below. EE431_microprocessor (.clk(clk),.reset(clear),.i_pins(stimulus[3:0]),.o_reg(cct_output[3:0]),.timer(timer) ); You must also modify the instantiation of student scrambler as shown below. The thing to notice is that an input to the student s scrambler is changed to include the effects of timer. student_scrambler scmblr_1(.clk(clk),.exam_number(exam_number),.scrambler_input(timer,cct_output[3:0]}),.scrambler_output(response) ); In making these modification you will have to declare any new wires used in exam test bench 2009 as wires. Compile project exam test bench Make sure the seed and exam number are is as shown in the answer table. Then simulate and record the value of accumulator output when counter full bar is 1 b0 on your answer sheet. (5) 4. Further modify your microprocessor to do the following: For this question you are to use same hex file that was used in question 3, which is Q3 and Q4.hex, to initialize your program memory. For this question, the ALU instruction referred to as no-operation 0, i.e. NOP0, will be referred to as read timer. Recall that there are two instructions associated with ALU function 3 b000 and that one of these is the no-operation instruction referred to as NOP0. Instruction NOP0 is now referred to as instruction read timer. Add a synchronous set-clear flip/flop called bingo to your microprocessor. The clear input overrides the set input on this flip/flop. This means if both the set and clear inputs are active at the time of a positive edge of the clock, the flip/flop

6 EE431 April 6, 2009 midterm 6 goes to 1 b0. bingo is cleared on all clock edges occurring while sync reset is active and it is also cleared on clock edges that execute the instruction read timer. bingo is set on the clock egde that decrements the timer from 4 b1 to 4 b0. Change the function of instruction NOP0, which is now called read timer, so that it does two things. It moves the contents of timer to the result register and it also moves the contents of flip/flop bingo to the zero flag flip/flop. This means that if bingo is set at the time a read timer instruction is executed the zero flag will be set, even though result register, which will be the value of timer, may not be a zero. In this is expected that your microprocessor s conditional jump logic is based on the zero flag and not the actual contents of the result register. If this is not the case, you will have to modify your conditional jump logic to make it so. After making the changes compile you microprocessor and complete the answer sheet.