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1 INTERNAL ASSESSMENT TEST 2 Date : 28/03/2016 Max Marks: 50 Subject & Code : Microprocessor (10CS45) Section: IV A and B Name of faculty: Deepti.C Time: 8:30-10:00 am Note: Answer any complete five questions 1. Explain the following instructions with an example: (10 Marks) i) XLAT This instruction converts the contents of AL register into a number stored in a memory table, this instruction perform the direct table look up technique often used to convert one code to another. An XLAT instruction 1st add the contents of this AL to BX to form a memory address within a data segment.it then copies the contents of this address into AL. This is the only instruction that adds an 8 bit number to 16-bit number. ii) LEA -LEA Register, Source This instruction determines the offset of the variable or memory location named as the source and puts this offset in the indicated 16-bit register. LEA does not affect any flag. LEA BX, PRICES Load BX with offset of PRICE in DS LEA BP, SS: STACK_TOP Load BP with offset of STACK_TOP in SS LEA CX, [BX][DI] Load CX with EA = [BX] + [DI] iii) CMP CMP Destination, Source This instruction compares a byte / word in the specified source with a byte / word in the specified destination. The source can be an immediate number, a register, or a memory location. The destination can be a register or a memory location. However, the source and the destination cannot both be memory locations. The comparison is actually done by subtracting the source byte or word from the destination byte or word. The source and the destination are not changed, but the flags are set to indicate the results of the comparison. AF, OF, SF, ZF, PF, and CF are updated by the CMP instruction. For the instruction CMP CX, BX, the values of CF, ZF, and SF will be as follows: CF ZF SF CX = BX Result of subtraction is 0 CX > BX No borrow required, so CF = 0 CX < BX Subtraction requires borrow, so CF = 1 CMP AL, 01H Compare immediate number 01H with byte in AL CMP BH, CL Compare byte in CL with byte in BH CMP CX, TEMP Compare word in DS at displacement TEMP with word at CX CMP PRICES [BX], 49H Compare immediate number 49H with byte at offset [BX] in array PRICES iv) MUL MUL Source This instruction multiplies an unsigned byte in some source with an unsigned byte in AL register

2 or an unsigned word in some source with an unsigned word in AX register. The source can be a register or a memory location. When a byte is multiplied by the content of AL, the result (product) is put in AX. When a word is multiplied by the content of AX, the result is put in DX and AX registers. If the most significant byte of a 16-bit result or the most significant word of a 32-bit result is 0, CF and OF will both be 0 s. AF, PF, SF and ZF are undefined after a MUL instruction. If you want to multiply a byte with a word, you must first move the byte to a word location such as an extended register and fill the upper byte of the word with all 0 s. You cannot use the CBW instruction for this, because the CBW instruction fills the upper byte with copies of the most significant bit of the lower byte. MUL BH Multiply AL with BH; result in AX MUL CX Multiply AX with CX; result high word in DX, low word in AX MUL BYTE PTR [BX] MUL FACTOR [BX] MOV AX, MCAND_16 Multiply AL with byte in DS pointed to by [BX] Multiply AL with byte at effective address FACTOR [BX], if it is declared as type byte with DB. Multiply AX with word at effective address FACTOR [BX], if it is declared as type word with DW. Load 16-bit multiplicand into AX v) LDS DI, [3000H]-- LDS Register, Memory address of the first word This instruction loads new values into the specified register and into the DS register from four successive memory locations. The word from two memory locations is copied into the specified register and the word from the next two memory locations is copied into the DS registers. LDS does not affect any flag. LDS DI, [3000H] Copy content of memory at displacement 3000H and 3001H in DS to DI, Copy content at displacement of 3002H and 3003H in DS to DS register.

3 2. What are assembler directives? Explain following assembler directives with an example Assembler directives are the commands to the assembler that direct the assembly process. They indicate how an operand is treated by the assembler and how assembler handles the program. They also direct the assembler how program and data should be arranged in the memory. The important point to be noted here is they do not generate any machine code i.e.they do not contribute to the final size of machine code (10 Marks) i) PUBLIC This directive is used to instruct the assembler that a Specified name or label will be accessed from other modules. Example: PUBLIC MULTIPLIER, INTEREST_RATE ii) ORG This directive instructs the assembler to start the program in memory from the offset mentioned in the argument of ORG. Example: ORG 100h will start the next instruction at an offset of 100h in the memory iii) DW DW declares a variable of type byte and reserves one location in memory for the variable of type word. Examples: num1 DW 1234h ARR1 DW 1A3Bh, 3A4Bh, 5A6CH ARR2 DW 50 DUP(0) iv) ASSUME. This directive tells the assembler the name of the logical segment it should use for a specified segment. For example ASSUME CS: CODE, tells the assembler that the instructions for a program are in a logical segment named CODE. The 8086 works directly with only 4 physical segments: a Code segment, a data segment, a stack segment, and an extra segment.

4 3. a) Write an ALP using 8086 instructions to search a number placed in location array of ten numbers placed at location ARRAY. Give suitable messages and comments..model SMALL.STACK.DATA ARR DW 0111H,0112H,0113H,0114H,0115H,0016H LEN DW ($-ARR)/2 KEY EQU 0115H MSG1 DB "KEY IS FOUND AT " RES DB " POSITION",13,10,"$" MSG2 DB 'KEY NOT FOUND!!!!!!!!!!!!!. $'.CODE MOV AX,@DATA ;Initialise data segment MOV DS,AX MOV BX,00 MOV DX,LEN ;Length of array MOV CX,KEY ;CX=Key AGAIN:CMP BX,DX ;Check length of array JA FAIL MOV AX,BX ADD AX,DX SHR AX,1 ;array length /2 MOV SI,AX ADD SI,SI ;Mid-element array index is found CMP CX,ARR[SI] ;compare key with arr[mid] JAE BIG DEC AX ;if key<arr[mid],mid=mid-1 MOV DX,AX JMP AGAIN ;repeat search BIG:JE SUCCESS INC AX ;if key>arr[mid],mid=mid+1 MOV BX,AX JMP AGAIN SUCCESS:ADD AL,01 ADD AL,'0' MOV RES,AL ;Key position LEA DX,MSG1 ;Display key found JMP DISP FAIL:LEA DX,MSG2 ;Display key not found DISP:MOV AH,09H INT 21H MOV AH,4CH ;End of program INT 21H END (8 Marks)

5 b)what is the status of 8086 flag bits after the addition of AX=30A2H with BX=F01CH(2 Marks) AX BX AX CF=1 ZF=0 SF=0 AF=0 PF=0 OF=1 4. Explain the functions of the following pins of 8086 microprocessor: (10 Marks) i) ALE :Address Latch Enable(Output) ALE is provided by the processor to latch the address into the 8282/8283 address latch. It is an active high pulse during T1 of any bus cycle. ALE signal is never floated. ii) INTR :Interrupt Request(Input) It is a level triggered input which is sampled during the last clock cycle of each instruction to determine if the processor should enter into an interrupt acknowledge operation. A subroutine is vectored to via an interrupt vector look up table located in system memory. It can be internally masked by software resetting the interrupt enable bit INTR is internally synchronized. This signal is active HIGH. iii) HOLD (I/O): Hold and Hold Acknowledge Hold indicates that another master is requesting a local bus "HOLD". To be acknowledged, HOLD must be active HIGH. The processor receiving the "HOLD request will issue HLDA (HIGH) as an acknowledgement in the middle of the T1-clock cycle. Simultaneous with the issue of HLDA, the processor will float the local bus and control lines. After "HOLD" is detected as being Low, the processor will lower the HLDA and when the processor needs to run another cycle, it will again drive the local bus and control lines. iv) RESET(I) Reset causes the processor to immediately terminate its present activity. To be recognised, the signal must be active high for at least four clock cycles, except after power-on which requires a 50 Micro Sec. pulse. It causes the 8086 to initialize registers DS, SS, ES, IP and flags to all zeros. It also initializes CS to FFFF H. Upon removal of the RESET signal from the RESET pin, the 8086 will fetch its next instruction from the 20 bit physical address FFFF0H. The reset signal to 8086 can be generated by the (Clock generation chip). To guarantee reset from power-up, the reset input must remain below 1.5 volts for 50 Micro sec. after Vcc has reached the minimum supply voltage of 4.5V.

6 v) BHE/S7(O): Bus High Enable/Status During T1 state the BHE should be used to enable data onto the most significant half of the data bus, pins D15 - D8. Eight-bit oriented devices tied to the upper half of the bus would normally use BHE to control chip select functions. BHE is Low during T1 state of read, write and interrupt acknowledge cycles when a byte is to be transferred on the high portion of the bus. The S7 status information is available during T2, T3 and T4 states. The signal is active Low and floats to 3- state during "hold" state. This pin is Low during T1 state for the 1st interrupt acknowledge cycle. 5. a) With diagram, explain RESET section of 8284 clock generator. Also indicate how CLOCK and RESET are connected to 8088 µp (8 Marks) The Reset section of the 8284A is very simple. It consists of a Schmitt trigger buffer and a single D-type flip flop circuit. The D-type flip flop ensures that the timing requirements of the 8086/8088 microprocessor RESET input are met. The circuit applies the RESET signal to the microprocessor negative edge (1-to-0 transition) of each clock. The 8086/8088 microprocessor sample RESET at the positive edge (0-to-1 transition) of the clocks; therefore, the circuit meets the timing requirements of the 8086/8088 microprocessor. The RC circuit provides logic 0 to the RES* input pin when power is first applied to the system. After a short time, the RES* input becomes a logic 1 because the capacitor charges toward +5.0V through the resistor. A push-button switch allows the microprocessor to be reset by the operator. Correct reset timing requires the RESET input to become logic 1 no later than four clocks after system power is applied and to be held high for at least 50µs. The flop-flop makes certain that RESET goes high in 4 clocks, and RC time constant ensures that it stays high for at least 50µs. The Reset logic generates the Reset input signal for the 8086/8088. When the RESET* pin goes low, the Reset output is generated by the 8284 when the next clock transition takes place.

7 b) Bring out differences between 8086 and 8088 microprocessors. (2 Marks) Features of the 8086: - A data width of 2 byte is attained by the de multiplexing of AD0 to AD15 pins. - The instruction queue is of 6 bytes. - From the memory the fetching of an instruction is performed only once there are 2 bytes empty in queue. - The BIU of 8086 is not as same as in the 8088 but the EU is similar. Features of the 8088: - It requires a 1 byte data width which is generated after the de multiplexing of AD0 to AD7 pins. - The instruction queue is 4-bytes. - Program fetching is performed as soon as there is a byte empty in queue. 6. Explain the timing diagram of read operation in 8086 microprocessor (10 Marks) During T1 state of a read machine cycle an 8086 first asserts the M/ IO signal. It will assert this signal high if it is going to read from memory during memory read cycle and it will assert M/ IO low if it is going to do a read from an input port during its read cycle. After asserting M/ IO, the 8086 sends out a high on the address latch enable signal, ALE. The microprocessor sends out on AD0-AD15, A16 through A19 and BHE lines, the address of the memory location that it wants to read. Since the latches are enabled by ALE being high, this address information passes through the latches to their outputs. The 8086 then makes the ALE output low. This disables the latches (8282) and holds the address information latched on the latch outputs. The address information latched on the latch outputs can now be used to select the desired memory or port location. Since the address information is now held on the latch, the 8086 does not need to send it out any more. The 8086 floats the AD0 - AD15 lines so that they can be used to input data from memory or from a port. At about the same time the 8086 also remove the BHE and A16-A19 information from the upper lines and sends out some status information on these lines. The 8086 is now ready to read data from the addressed memory locations or port.

8 During T2-state the 8086 asserts its RD signal low. This signal is used to enable the addressed memory device or port device. At the end of T3 state the microprocessor makes RD signal high and reads the data available on the data bus, provided the READY input signal is high. If the READY input pin is not high at the sampled time in a machine cycle, the 8086 will insert one or more WAIT states between T3 and T4 states in that machine cycle. An external hardware device is set up to pulse READY low before the rising edge of the clock in T2 state. After the 8086 finishes T3 of the machine cycle, it enters a WAIT state.if the READY input is still low at the end of a WAIT state, then the 8086 will insert another WAIT state. The 8086 will continue inserting WAIT states until the READY input is sampled high again. If the READY input is sampled high again during T3 or during the WAIT state, the microprocessor comes out of the WAIT state and will initiate T4 of the machine cycle. The DEN signal is used to enable bi-directional buffers on the data bus. The data enable signal, DEN, from the 8086 will enable the data buffer when it is asserted LOW. The data transmit / receive signal DT/ R from the 8086 is used to specify the direction in which the buffers are enabled. When DT/ R is asserted high, the buffers will, if enabled by DEN, transmit data from the 8086 to Memory or I/O ports. When DT/ R is asserted low, the buffers, if enabled by DEN, will allow data to be received from Memory or I/O ports of the DT/ R is asserted during T1 of the machine cycle. The DEN is asserted after the 8086 finishes using the data bus to send the lower 16 address bits * * * * * * *

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VENUS INTERNATIONAL COLLEGE OF TECHNOLOGY Gandhinagar Department of Computer Enggineering ADVANCE MICROPROCESSOR & INTERFACING Name : Enroll no. : Class Year : 2014-15 : 5 th SEM C.E. VENUS INTERNATIONAL