CS222: Dr. A. Sahu. Indian Institute of Technology Guwahati
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1 CS222: (a) Activation Record of Merge Sort (b) Architecture Space RISC/CISC Dr. A. Sahu Dept of Comp. Sc. & Engg. Indian Institute of Technology Guwahati 1
2 Outline Activation Record in Recursion: Merge Sort Activation Record Features of MIPS ISA Other architectural variations RISC and CISC Examples
3 Activation record / frame $sp local data saved s registers (if any) return addr $fp arguments
4 const m = 20; Sorting example Main void main(void) { int N, i; int X[m], Y[m]; } cout << "enter the count of integers\n"; cin>> N; cout << "enter the integers\n"; for (i= 0; i< N; i++) cin >> X[i]; sort(x, Y, N); cout << "sorted values : \n"; for (i = 0; i< N; i++) cout << Y[i] << " "; cout << endl;
5 Recursive merge sort procedure void sort (int A[ ], int B[ ], int n) { } int A1[m], A2[m]; int n1, n2; if (n == 1) B[0] = A[0]; else { } n1 = n / 2; n2 = n n1; sort (A, A1, n1); sort (A+n1, A2, n2); merge (A1, A2, B, n1, n2);
6 Merge procedure void merge (int P[ ], int Q[ ], int R[ ], int p, int q) { } int i, j, k; i= j = k = 0; while (i < p && j < q) if (P[i] < Q[ j]) R[k++] = P[i++]; else R[k++] = Q[ j++]; while (i < p) R[k++] = P[i++]; while (j < q) R[k++] = Q[ j++];
7 Activation record for merge void merge (int P[ ], int Q[ ], int R[ ], int p, int q) { int i, j, k;.. } $sp i j k return addr P Q R p q s lo cals para ameter
8 Simplifying activation record $sp i j k return addr P Q R p q $sp return addr p q a0 P a1 Q a2 R t0 i t1 j t2 k
9 Activation record for sort void sort (int A[ ], int B[ ], int n) { } int A1[m], A2[m]; int n1, n2; $sp A1 A2 n1 n2 return addr A B n locals pa aramet ters
10 Part of merge procedure.. while (i < p) R[k++] = P[i++]; a0 a1 a2 t0 t1 t2 return addr p q P Q R i j k lw $t3, 4($sp) L: bge $t0, $t3, X muli $t4, $t0, 4 add $t4, $t4, $a0 lw $t6, 0($t4) addi $t0, $t0, 1 muli $t5, $t2, 4 add $t5, $t5, $a2 sw $t6, 0($t5) addi $t2, $t2, 1 j L X:
11 Calling merge return addr p q A1 A2 n1 n2 return addr A B n merge (A1, A2, B, n1, n2); addi $a0, $sp, 0 addi $1$ $a1, $sp, 80 lw $a2, 176($sp) lw $t8, 160($sp) P sw $t8, 8($sp) 1 Q lw $t8, 164($sp) R sw $t8, 4($sp) i addi $sp, $sp, 12 j jal merge k. merge: sw $ra, 0($sp) a0 a1 a2 t0 t1 t2
12 Return from merge return addr p q A1 A2 n1 n2 return addr A B n a0 a1 a2 t0 t1 t2 P Q R i j k lw $ra, 0($sp) addi $sp, $sp, 12 jr $ra
13 Calling sort sort (A, A1, n1); A B sort: sw $ra, 168($sp) n. A1 lw $t8, 172($sp) A2 n1 n2 return addr A B n sw $t8, 12($sp) addi $t8, $sp, 0 sw $t8, 8($sp) lw $t8, 160($sp) sw $t8, 4($sp) addi $sp, $sp, 184 jal sort
14 A B n A1 A2 n1 n2 return addr A B n Return from sort lw $ra, 168($sp) addi $sp, $sp, 184 jr $ra
15 Further work (lab exercise) Complete the assembly program for recursive merge sort Write a pointer version (C and assembly) Include code to track the max stack size Reduce local arraysizeto n and find improvement Write more space efficient program (C and assembly), still recursive
16 Architecture Space Features of MIPS ISA Other architectural variations RISC and CISC Examples 16
17 What constitutes ISA? Main features: Set of basic/primitive operations Storage structure registers/memory How addresses are specified How instructions are encoded
18 MIPS ISA features operations Arithmetic Logical Relational l Branch/jump Data movement Procedure linkage
19 MIPS ISA features storage 0 1 Registers 0 4 Memory
20 MIPS ISA features addressing Purpose Operand sources Result Destinations Jump targets Addressing modes Immediate Register Base/index PC relative (pseudo) Direct Register indirect
21 MIPS addressing modes 1 Immediate addressing op rs rt constant Register addressing op rs rt rd func 0 1 Registers 31
22 MIPS addressing modes 2 Base addressing 0 op rs rt constant 4 Memory op rs register + data PC relative addressing rt constant PC + instruction
23 MIPS addressing modes 3 (pseudo) Direct addressing 0 op constant 4 Memory op rs rt PC + instruction Register indirect addressing rd func Register instruction
24 MIPS ISA features encoding addi, lui, beq, bne, lw, sw I format op rs rt 16 bit number j, jal op 26 bit number add, jr J format R format op rs rt rd shamt funct
25 MIPS ISA features summary All instructions of same size Only 3 formats Fair number of GP registers Simple operations either arith/logic or memory access or control transfer Limited addressing modes Separate fields for src1, src2 and dest
26 Alternative Architectures Provide more powerful operations e.g. J++ and branch to L if J>N, where J is in memory or copy a block of data in memory Goal is to reduce number of instructions executed Danger is a slower cycle time and/or a higher CPI
27 Location of operands R/M R R R M M M M R+M Both operands in registers one operand in register and one in memory Both operands in memory Combines R R, R M and M M
28 How many operand fields? 3 address machine 2 address machine 1 address machine 0 address machine r1 = r2 + r3 r1 = r1 + r2 Acc = Acc + x Acc is implicit add values on top of stack
29 Register organizations Register less machine Accumulator based machine A few special purpose registers Several general purpose registers Large number of registers / register windows
30 Additional addressing modes Direct Indirect Base vs. Index Auto increment and auto decrement Pre (post) increment/decrement Stack
31 RISC vs. CISC Reduced (vs. Complex) Instruction Set Computer Uniformity of instructions Simple set of operations and addressing modes Register based architecture with 3 address instructions
32 RISC Philosophy 1970s John Cocke at IBM Majority of combinations of orthogonal addressing modes and instructions were not used By most programs generated tdby compilers Difficult in many cases to write a compiler To take advantage of the features provided by conventional CPUs. 32
33 RISC examples Virtually all new instruction sets since 1982 have been RISC SUN s SPARC (Scalable Processor ARChitecture) HP s PA RISC ARM (Advance RISC Machine) Motorola s PowerPC (Performance Optimization With Enhanced RISC Performance Computing,) DEC s Alpha MIPS CDC 6600 (1960 s)
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