ECT 224: Digital Computer Fundamentals Using Xilinx StateCAD

Transcription

1 ECT 224: Digital Computer Fundamentals Using Xilinx StateCAD 1) Sequential circuit design often starts with a problem statement tat can be realized in the form of a state diagram or state table a) Xilinx offers the StateCAD application to be used within the Xilinx ISE framework to provide a graphical implementation of a state diagram. 2) Open Xilinx ISE 9.1 (the Xilinx integrated development environment) 3) Open a project or create a new project (remember no spaces in path or project name) a) This tutorial is going to assume that the project being used has a top level schematic. 4) Create a StateCAD source file for this project a) In the Sources window select the Synthesis/Implementation option for the Sources for: category. b) Right-click on the project name in the Sources window and select the option to New Source c) In the New Source Wizard window select the State Diagram option and provide a meaningful name for this source file as shown in Figure 1, and finally select the Next and Finish options. Figure 1: New source window setup for adding a state diagram 5) The StateCAD application opens in a new window with the new source file (*.dia) as shown in Figure 2. Figure 2: StateCAD application window for new source

2 6) Select the Start State Machines option ( ) to start the State Machine Wizard as shown in Figure 3. a) Select the Geometric option and input the desired number of states for the sequential circuit and then select the Next option Figure 3: State Machine Wizard 7) Recall that the Xilinx Spartan-II FPGA has asynchronous reset capabilities; therefore select asynchronous as the reset mode as shown in Figure 4 and the n select the Next option. Figure 4: Selecting the reset method for the state machine 8) To setup the transitions from one state to another, select both the Next and Previous options in the Setup Transitions window as shown in Figure 5 and then select the Finish option Figure 5: Setup transitions window for each state in state machine

3 9) The template state diagram has been created and must now be placed onto the blank diagram window. Placing the diagram in the top left corner of the diagram window is a good location for the state diagram as shown in Figure 6. Figure 6: StateCAD diagram window with new state machine diagram 10) Once the state diagram is placed, inputs to the state diagram can be added. a) Select the Add Vector option ( ) from the left-side toolbar and place a vector below the placed state diagram. b) Double click the new vector and modify its parameters such as name a size as shown in Figure 7. Figure 7: Parameter editing for input vector 11) The state diagram s current transitions can be removed modified or new transitions can be added. a) Left-click on any transition to access the Edit transitions window as shown in Figure 8. i) Conditions can be added in the Condition: entry box per input requirements for the transitions (Mode input must be true or 1 as shown in Figure 8) ii) To select the correct output of the transition, click on the Output Wizard button. Select the Constant option from the upper left box, type in the name of the output signal in the DOUT box along with the associated width of the output data path. The output value for the given transition is then entered in the CONSTANT box. The Logic Wizard window shown in Figure 9 depicts the settings for a transition with the 4-bit constant output Q that has a value of 9. iii) After all input and output values have been set for the selected transition select the OK option within the Edit Conditions window. The transition parameter will now be displayed on the state diagram window.

4 Figure 8: Setting an input for a state transition Figure 9: Assigning output values for state transition 12) Continue modifying all transitions until the desired state diagram implementation is completed. a) Once the state diagram is complete, it must be exported to either VHDL or Verilog code for final implementation into the project s top-level schematic b) Select the Generate HDL option ( ) and make sure that Verilog option is selected (as shown in the top right of the StateCAD window shown in Figure 2). 13) To perform a behavior simulate of the state diagram, the StateCAD program contains a simulation tool called StateBench a) Select the StateBench option ( ) to start the simulator as shown in Figure 10. b) To reset the state machine use the Reset button ( ). c) To add a new clock period to the simulation use the Cycle button ( ). d) To modify the value of the input vectors, double click on the input signal and modify its value as shown in Figure 11. e) Make sure to save the designed StateBench using the Save TestBench button ( ). f) To execute the StateBench use the Run TestBench option ( ).

5 Figure 10: StateBench simulator window Figure 11: Panel to modify input vector value for StateBench simulator 14) Back in the Xilinx ISE the new Verilog file generated from the StateCAD application must be added to the project. a) In the Sources window select the Synthesis/Implementation option for the Sources for: category. b) Right-click on the project name in the Sources window and select the option to Add Source c) In the Add Existing Sources window select the Verilog file (*.v) with the same name as the StateCAD diagram (*.dia) and select the Open options. d) Highlight the added Verilog source file and in the Processes window select the Create Schematic Symbol from the Design Utilities category. 15) To insert the new symbol into the top-level schematic, change the Category option to the project s working directory from within the Sources window when the Symbols tab is selected as shown in Figure 12. Figure 92: Selecting the new symbol for insertion into the project