Getting started with the Xilinx Project Navigator and the Digilent BASYS 2 board.
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1 Getting started with the Xilinx Project Navigator and the Digilent BASYS 2 board. This lab is based on: Xilinx Project Navigator, Release Version 14.6 Digilent Adept System Rev 2.7, Runtime Rev 2.16 Digilent Basys2 100 Project board Credit to the University of Oklahoma for the original download of this lab. To start: Open Xilinx Project Navigator (ISE Design Suite) Select a new project [File at top left and select new project] Enter a new project name and select the storage location as the Desktop Choose 'HDL' as the top-level source type for the project Select NEXT Check that all of the boxes are selected exactly like the following list: Evaluation Development Board: (default) None Specified Product category: (default) All Family: Spartan3E Device: XC3S100E Package: CP132 Speed: -4 Top-level source type: HDL (grayed) Synthesis tool: (default) XST (VHDigilentDL/Verilog) Simulator: (default) ISim (VHDLNerilog) Preferred language: (default) VHDL Property Specification in Project File: (default) Store non-default values only Manual Compile Order: (default) unchecked VHDL Source Analysis Standard: VHDL-93 Enable Message Filtering: (default) unchecked Select NEXT A summary of the settings is displayed, Click FINISH to complete.
2 Add a source schematic with the "New Source Wizard". There are three ways to open the New Source Wizard. 1) Right click on the chip name and select "New Source" 2) In the "Project" drop down in the top navigation bar, select "New Source". 3) On the left side of the screen there are two vertical selection bars, the selection bar on the far left selects the role of the next menu bar to the right. In general you should stay in the DESIGN role. When in the design role, the first icon at the top of the next column is the NEW SOURCE icon. The "New Source Wizard" window will open (shown above). >Select source type Schematic and provide a name for the schematic. >Accept the default directory. This schematic will be placed in the current project directory. >Click NEXT and the summary appears. >Check that this is what you intend. If all is well, click FINISH. You will now see your schematic in the hierarchy below your chip. Now you can draw the schematic!
3 The first step to creating the schematic is to add symbols. There is a vertical icon bar just to the left of the schematic drawing area. About half way down the bar is the icon to add symbol. When you click on the icon, two lists appear to the left. The first list is the categories of symbols. The first item in this list is all symbols. The second window down lists all of the symbols in that category. The symbols appear very small so use the ZOOM tool at the top of the page to zoom in and make them bigger. Add the following list of symbols as shown in the screen shot below: And3 under logic Or3 under logic
4 The next step is to add input and output buffers. In schematic design, each input must have an input buffer (ibuf) and each output needs an output buffer (obuf). Input and output buffers are added as symbols. They are found under IO symbol group. Add the buffers as shown in the screen shot below:
5 The next step is to add wires to connect the devices. Add wires as shown in the screen shot below:
6 The next step is to add IO markers to all of the input and output buffers. The icon just above the add symbols icon is the IO markers icon. The default is to add automatically numbered markers. Put the mouse pointer on each of the inputs, right click and drag to the left, then release. Do the same thing with the outputs but instead drag to the right. Each of the input and output buffers should have markers as shown below. Click on the SELECT icon at the top of the vertical row of icons. Select each IO marker and rename each of the markers by doing a right click on the marker and selecting RENAME PORT. Give each port the names as shown below.
7 Test the schematic design for problems. Make sure you are in the DESIGN tab on the far left side of the screen. With the *.sch file highlighted in the "sources" window, go to the "processes" window and right click on "check design rules" under "design utilities" (you may need to expand this item) from the pop-up menu select "run" or "rerun." Errors will be indicated in the "console" window at the bottom. Next assign the I/O port to the XC3S100E package pins. With the *.sch file highlighted in the "sources" window, go to the "processes" window, expand the USER CONSTRAINTS item and right click on "Floor - plan Area/IO/Logic (Plan Ahead)" select "run" or "rerun." Double clicking will also work. If this is the first time to assign pins in this project you will get a message "This process requires that an Implementation Constraint File (UCF) be added..." click yes to create one. A new window "Plan Ahead" will open with a diagram of the XC3S100E among other windows. Wait for the program to fully load. This takes a while. The important part is the table at the bottom "showing the I/O ports named as in your schematic and the "I/O Port Properties" window above it. Select the port to assign in the "I/O Ports Window". You may need to expand "all ports" and "scalar ports". The selected port will appear in the I/O Ports Properties window. Click on the box for the input under the site column. Look at the Basys 2 board and decide which switches and LEDS that you want to assign to the I/O. Look at the designation under each of the switches or LEDS. Enter the pin assignment in the "site" box and hit return. The I/O ports table will update with the new pin assignment. After you have assigned all your pins, chose "Save constraints" from the "File" drop down menu. You can close the Plan Ahead window. UCF files are simple text files. You may find it easier to manipulate them using a. text editor once you have a UCF file generated that you can use as a template. Be careful. The format and syntax are rigid. So a typo will probably cause your design to fail. You can now generate the programming file. With the *.sch file, highlighted in the "sources" window, go to the "processes" window and right click on "Implement Design" and select "run" or "rerun". IF you expand the Implement design pull down you should have green boxes next to each of the items. Next, double click on the Generate Programming File text. When it completes, there should be a green check next to it and the Console window should say: Process "Generate Programming File" completed successfully. The Design Summary Window contains a summary of the result, along with lots of other statistics. If all goes well, a green check mark will appear beside the "Implement Designs" and "Generate Programming File". You should have no errors. Errors are fatal for the program file generation process. Warnings are alerts that something might be wrong with your design (e.g. ports not assigned to pins), but are not fatal.
8 Programming the Basys2 board using the USB cable. Before attempting to program using the USB cable, the board must be set up properly. 1) Set the shunt on JP3 to "PC" (bridge the 2 pins on the side marked "PC"). Connect the board to your computer using the USB cable and turn the power switch on the Basys2 board to the "on" position". The red power LED (LD-8) should light. Open "Adept" the program. Adept should autodetect the USB device (this is the default), e.g. Connect: "Onboard USB", product: "Basys2-100". If it doesn't, make sure the power switch on your Basys2 board is in the "on" position. To program your board, open the "Config" tab. In order to proceed, you must have already generated the.bit programming file in the Xilinx Project Navigator. The.bit file can be programmed into either the volatile FPGA- RAM or the non-volatile PROM (Platform Flash). Click on "Browse", then navigate to the.bit file you have created, which will be in your Desktop. After selecting the file, it will appear in the drop-down box. Click on the "Program" button at the right to program the Basys2 board. If you load your.bit file into the FPGA, your program it will begin running immediately after programming is complete. Programs stored in the FPGA will be erased when the Basys2 is powered off.
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