TUTORIAL On USING XILINX ISE FOUNDATION DESIGN TOOLS: Mixing VHDL and Schematics

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1 TUTORIAL On USING XILINX ISE FOUNDATION DESIGN TOOLS: Mixing VHDL and Schematics Shawki Areibi July 7, Introduction The objective of this tutorial is to show how VHDL can be incorporated into a schematic design using the ISE tools. At this point, the student should have read and understood the following documents: 1. TUTORIAL ON USING XILINX ISE FOUNDATION DESIGN TOOLS: Design Entry Using Schematic Capture 2. TUTORIAL ON USING XILINX ISE FOUNDATION DESIGN TOOLS: Design Entry Using VHDL Students should also be familiar with the Engineering Capture System (ECS) and the Test Bencher software. 2 Starting a new project Since we wish to combine VHDL with schematic capture, we will create a new project with schematic as the Top-Level Module Type. 1. Load the Project Navigator from the Programs Xilinx ISE The Project Navigator window will appear. Select File New Project 3. The New Project dialog box will appear. Specify the directory in which you want to store the project in and give the project a name. In the Top-Level Module Type section select Schematic and click Next. 4. Another New Project dialog box will appear prompting you for device, synthesis and simulation settings for the project. 1

In this dialog box verify the following settings: Device Family Spartan2E. Device xc2s200e. Package pq208. Speed Grade -6. Synthesis Tool XST (VHDL/Verilog). Simulator Modelsim.

2 In this dialog box verify the following settings: Device Family Spartan2E. Device xc2s200e. Package pq208. Speed Grade -6. Synthesis Tool XST (VHDL/Verilog). Simulator Modelsim. Generated Simulation Language VHDL. If the information is correct click Next. 5. The next dialog box will ask if you wish to add a new source file to the project. Click New Source... A new dialog box will appear prompting you for the file type, name and location. Select VHDL module from the list of file types and name the file MyAdder (Project Navigator will append the appropriate file extension). The default location should be the project directory and ensure the Add to project box is checked. 6. In the Define VHDL Source dialog box that appears, add ports A, B and CI as inputs and CO and S as outputs. Click Next when this is done. 7. The next dialog box will allow you to confirm the previous choices. Click if they are correct. 8. You will now return to the New Project dialog box and the MyAdder.vhd source template that you have created will now be listed. Click Next. The next dialog box is used to add existing source files to the project. Since we are only using new source files in this project, click Next. Finally, a confirmation dialog box will appear. Click Finish if the information is correct. 2

3 3 Using the HDL Editor for VHDL We are now ready to start working with the HDL Editor. 1. At the completion of the last section the VHDL editor window should now have the template code with the variables that you entered. Modify the code to match the following: 1 bit Full Adder use IEEE.std logic 1164.all; entity fulladd is A, B, Ci: in STD LOGIC; Co, S: out STD LOGIC end fulladd; architecture fulladd arch of fulladd is S ((A xor B) xor Ci Co ((A and B) or (Ci and (A xor B)) end fulladd arch; 4 bit Adder use IEEE.std logic 1164.all; entity adder4 is A0,A1,A2,A3: in STD LOGIC; B0,B1,B2,B3: in STD LOGIC; Ci: in STD LOGIC; Co: out STD LOGIC; S0,S1,S2,S3: out STD LOGIC end adder4; architecture adder4 arch of adder4 is COMPONENT fulladd A, B, Ci: in STD LOGIC; Co, S: out STD LOGIC END COMPONENT; signal tmp: STD LOGIC VECTOR (2 downto 0 3

U0: fulladd port map(ci Ci, A A0,B B0,S S0,Co tmp(0) U1: fulladd port map(ci tmp(0),a A1,B B1,S S1,Co tmp(1) U2: fulladd port map(ci tmp(1),a A2,B B2,S S2,Co tmp(2) U3: fulladd port map(ci tmp(2),a

4 U0: fulladd port map(ci Ci, A A0,B B0,S S0,Co tmp(0) U1: fulladd port map(ci tmp(0),a A1,B B1,S S1,Co tmp(1) U2: fulladd port map(ci tmp(1),a A2,B B2,S S2,Co tmp(2) U3: fulladd port map(ci tmp(2),a A3,B B3,S S3,Co Co end adder4 arch; 2. We must now check that the syntax of the VHDL code is correct. In the Project Navigator window highlight the VHDL source in the Sources in Project pane. Expand if it is not already and double click A process will be spawned to verify the VHDL code for syntax errors. If there are none, a green check mark will appear next to the Check Syntax process. If errors where found, A red cross will appear next to the Check Syntax process. The errors will be listed in the Errors tab of the Transcript window located at the bottom of the Project Navigator window. In it you will see a listing of the errors and the lines on which they occur. If you double click on an error message a red dot will appear in the VHDL editor pane next to (or close to) the line where the error was found. 3. Once you have eliminated all of the errors, save your work. 4. We will now create a module that can be used in the Schematic Editor. Expand the if it is not already and double click. If the process is successful a green check will appear next to the process name. Output from the process is shown in the Transcript window at the bottom of the Project Navigator window. We are now ready to use the symbol in a schematic. 4 Using the macro Now return to the Project Navigator and add a schematic source to the project. In the Symbols tab of the Options toolbar, the project directory will be listed in the Catagories pane. Highlight this entry and the adder4 symbol that you have created will be listed in the Symbols pane. You can use it in the same way you use the other components. 4

5 5 APPENDIX VHDL code for an 8 function ALU built from the 4 bit adder circuit bit Full Adder use IEEE.std_logic_1164.all; entity fulladd is A, B, Ci: in STD_LOGIC; Co, S: out STD_LOGIC end fulladd; architecture fulladd_arch of fulladd is S <= ((A xor B) xor Ci Co <= ((A and B) or (Ci and (A xor B)) end fulladd_arch; -- 4 bit Adder with carry propagation control use IEEE.std_logic_1164.all; entity adder4 is A,B: in STD_LOGIC_VECTOR (3 downto 0 Ci, CP: in STD_LOGIC; --CP controls propagation of carry bits Co: out STD_LOGIC; S: out STD_LOGIC_VECTOR (3 downto 0) end adder4; architecture adder4_arch of adder4 is COMPONENT fulladd A, B, Ci: in STD_LOGIC; Co, S: out STD_LOGIC END COMPONENT; signal tmp: STD_LOGIC_VECTOR (2 downto 0 signal CS: STD_LOGIC_VECTOR (3 downto 0 5

6 CS(0) <= Ci and CP; U0: fulladd port map (Ci=>CS(0),A=>A(0),B=>B(0),S=>S(0),Co=>tmp(0) CS(1) <= tmp(0) and CP; U1: fulladd port map (Ci=>CS(1),A=>A(1),B=>B(1),S=>S(1),Co=>tmp(1) CS(2) <= tmp(1) and CP; U2: fulladd port map (Ci=>CS(2),A=>A(2),B=>B(2),S=>S(2),Co=>tmp(2) CS(3) <= tmp(2) and CP; U3: fulladd port map (Ci=>CS(3),A=>A(3),B=>B(3),S=>S(3),Co=>Co end adder4_arch; -- B bit manipulation for ALU functions use IEEE.std_logic_1164.all; entity Bmod is A,Bin: in STD_LOGIC; S: in STD_LOGIC_VECTOR(2 downto 0 Bout: out STD_LOGIC end Bmod; architecture Bmod_arch of Bmod is signal I: STD_LOGIC_VECTOR (4 downto 0 I(0) <= A; I(1) <= Bin; I(2) <= S(0 I(3) <= S(1 I(4) <= S(2 with I select Bout <= 1 when "00010", 1 when "00011", 1 when "01000", 1 when "01001", 1 when "01101", 1 when "10010", 1 when "10110", 1 when "10111", 1 when "11000", 1 when "11001", 1 when "11010", 1 when "11011", 6

7 1 when "11100", 1 when "11111", 0 when others; end Bmod_arch; -- 4 bit ALU -- I(3-0) Operation add A and B increment A subtract B from A AND A and B OR A and B XOR A and B invert A invert B NOTE: Selection bits I0 and I1 must be go into an OR gate which -- is connected to the Ci of the first stage of the ALU. This -- is to provide the additional bit needed for the increment A -- and subtract B (two s compliment) operations. -- use IEEE.std_logic_1164.all; entity ALU is A,B: in STD_LOGIC_VECTOR (3 downto 0 I: in STD_LOGIC_VECTOR (2 downto 0 --operation selection Ci: in STD_LOGIC; Co: out STD_LOGIC; S: out STD_LOGIC_VECTOR (3 downto 0) end ALU; architecture ALU_arch of ALU is COMPONENT adder4 A,B: in STD_LOGIC_VECTOR (3 downto 0 Ci,CP:in STD_LOGIC; -- CP controls the propagation of carry bits Co: out STD_LOGIC; S: out STD_LOGIC_VECTOR (3 downto 0) END COMPONENT; COMPONENT Bmod 7

8 A, Bin: in STD_LOGIC; S: in STD_LOGIC_VECTOR(2 downto 0 Bout: out STD_LOGIC END COMPONENT; signal tmp: STD_LOGIC_VECTOR (3 downto 0 signal CPtmp: STD_LOGIC; CPtmp <= ((I(2) nor I(0)) or (I(1) nor I(2)) U0: Bmod port map (A => A(0), Bin => B(0), S => I, Bout=>tmp(0) U1: Bmod port map (A => A(1), Bin => B(1), S => I, Bout=>tmp(1) U2: Bmod port map (A => A(2), Bin => B(2), S => I, Bout=>tmp(2) U3: Bmod port map (A => A(3), Bin => B(3), S => I, Bout=>tmp(3) U4: adder4 port map (CP=>CPtmp,Ci=>Ci,A=>A,B => tmp, S=>S, Co=>Co end ALU_arch; 8

Logic Implementation on a Xilinx FPGA using VHDL WWU Linux platform assumed. rev 10/25/16

1 Logic Implementation on a Xilinx FPGA using VHDL WWU Linux platform assumed. rev 10/25/16 The following is a general outline of steps (i.e. design flow) used to implement a digital system described with