Introduction to Verilog and XILINX

Transcription

1 DEPARTAMENTO DE TECNOLOGÍA ELECTRÓNICA ESCUELA TÉCNICA SUPERIOR DE INGENIERÍA INFORMÁTICA Introduction to Verilog and XILINX Lab Session Computer Structure WARNING: A written solution of the preliminary work is required to carry out the laboratory session. A written solution will be presented per person and given to the instructor during the session. The solution must answer all the issues and must be detailed, complete, clear and well presented. The teacher can ask questions or seek clarification on the solution. Each student must bring a hard copy of this document. 1. Introduction One of the main goals of this subject is learning the design methodology of digital systems at register transfer level. We will apply the methodology learned at class in this session in order to: get used to the Verilog-HDL language. learn an FPGA based design environment. We will use the environment provided by XILINX 1. learn the design verification tools. carry out the design and simulation of circuits. One of them will be combinational (a code converter) and the other one will be sequential (a counter). 2. Preliminary work You must describe the following components using Verilog: 1. A converter from binary to seven-segment 2. A rising 4-bit counter Code templates have been prepared for both circuits. The following text files will be available to carry 1 Xilinx Inc.: a technology company supplier of programmable logic devices ( rev. 248

2 Computer Structure 2 out the session: File name Content Description convertidor.v convertidor_tb.v contador.v Module describing the sevensegment converter Testbench for the seven-segment converter Module describing the 4-bit counter You must complete this before the lab session. You will use this to simulate the converter. You must complete this before the lab session. contador_tb.v Testbench for the 4-bit counter You will use this to simulate the counter. lab2.v lab2_tb.v Structural description of a system using the previous modules Testbench of the whole system You must complete this during the lab session. You will use this to simulate the whole system. Table 1. Files to be used during the lab session The circuits to be described in Verilog are detailed below: 2.1. Designing the seven-segment converter Seven-segment displays are used to display decimal digits and some letters. This displays have seven inputs, one for each of it segments. The signals controls which segments are highlighted. By selecting which segments are highlighted several characters can be displayed. For example, every decimal digit can be displayed as shown in fig. 1. Figure 1. Decimal digits in a seven-segment display The truth table of the combinational circuit to be described is shown at table 2. The names of the segments in the table are the same of those in fig. 1. A segment will be highlighted if an only if the corresponding control signal is low. The displayed character will be the hexadecimal representation of the input.

3 Computer Structure 3 bin 3 bin 2 bin 1 bin 0 A B C D E F G Table 2: Truth table for the binary to seven-segment converter The circuit can be described with a case statement. Complete the following template to make the Verilog description (file convertidor.v): module convertidor_bin7seg( input [3:0] bin_in, // entrada binaria 4 bits output reg a,b,c,d,e,f,g); // salida 7-segmentos // Write your code here. // You are advised to use procedural description // containing a case statement. endmodule Code 1. File convertidor.v: Verilog code template for the converter 2.2. Designing the four-bit counter The counter will be triggered by the rising edge of the clock signal. It will a synchronous input RESET signal and a terminal count signal (CY). Its behaviour is detailed in fig. 2b. Complete the template code 2 (file contador.v) to make the Verilog description.

4 Computer Structure 4 CLK RESET UP CONT 1 X CONT 0 UP RESET CONT MOD 16 CY 0 1 CONT CONT CONT CONT CY CLK q3 q2 q1 q0 0 [CONT] [CONT] = 1111 (a) (b) Figura 2. Description of the four-bit counter: (a) structural description, (b) functional description module contador_mod16( input clk,up,reset, output reg [3:0] q, output cy); // Write your code here. // Remember: cy must be equal to one if and // only if the counter is in the last state endmodule Code 2. File contador.v: Verilog code template for the counter 3. Lab work In this session you will use Xilinx ISE tools to simulate the system you have designed. You will use the provided testbench files. To do so do the following: 1. Follow the Xilinx ISE tutorial of the next section to create a project called PracticaEdC2 including the files of the preliminary work. 2. Use the provided testbench (file convertidor_tb.v) to simulate the converter as described in the appendix. Check if the converter works as expected. 3. Use the provided testbench (file contador_tb.v) to simulate the counter as described in the appendix. Check if the counter works as expected. 4. Note that in the counter simulation the terminal count signal is never activated. Change the testbench file so at least a complete count cycle is simulated and check it. 5. Complete the template code 3 (file lab2.v) to make the Verilog description of a system containing an instance of both circuits interconnected. 6. Use the provided testbench (file lab2_tb.v) to simulate the previous system as described in

5 Computer Structure 5 the appendix. Check if it works as expected. module lab2( input clk, up, reset, output [0:6] seg, output cy); // Declare a bus to connect the counter // output and the converter input // instantiate the counter and // connect its i/o signals // instantiate the converter and // connect its i/o signals endmodule // lab2 Code 3. File lab2.v: Verilog code template for the whole system. 4. Xilinx ISE tutorial This section describes the XILINX ISE environment. The environment includes a Verilog logic analyzer that we will use in this session Creating a project After launching the ISE environment you must select the option New Project of the File menu. The window depicted at fig. 3 will pop-up. Fill in the name of the project (PracticaEdC2 for example). A folder with that name will be created. Every file related to the project will be saved there. Now press the Next button. The dialogue box depicted in fig. 4 will pop up. Set every option displayed as follows: Family: Spartan 3E Device: XC3S100E Package: CP132 Preferred Language: Verilog Left the remaining options with their default value as shown in fig 4. Press the Next button and a new window will pop-up. Click on the Finish button to create the project. Fig. 5 depicts the environment window after creating the project.

6 Computer Structure 6 Figure 3. Figure 4. Figure 5. Note the view options above the project name, Implementation and Simulation (fig. 5). You must choose the simulation view. If the frames or controls are not properly displayed click on Layout Restore Default Layout Adding files to the project After creating the project you must add the Verilog files (design and testbenchs). To do so you can use the corresponding option of the Project menu or rigth-click on the empty frame of the project view.

7 Computer Structure 7 You must choose between the Add copy of source and the Add Source options. If the first option is selected, ISE will create within the project folder a copy of the selected file so the original file will not be modified. If the second one is selected, the original selected file will be added to the project, and it could edited within the ISE framework. The New source just create a new empty file. You are advised to choose the Add Source option to add files to the project. You will have to specify witch files are used for the implementation and which are just used for simulation (the supplied testbench files). Fig. 6 shows how the files must be associated in order to carry out the simulation successfully. Figure 6. Once the files have been added they are shown in a hierarchical tree showing their dependences as depicted in fig. 7. To edit or watch any of the project file you just have to double left-click on its name Simulating and verifying a design Testbench files make it possible to verify the functionality of a design by simulating its behaviour. The testbench files of a project are displayed in the simulation view, not in the implementation view, since they are just used to carry out simulations. The hierarchical file tree is not the same in both views, as shown in fig. 7.

8 Computer Structure 8 Figure 7. Figure 8. In order to simulate a design you must select the file containing its testbech. Then you must double-click the Simulate Behavioural Model option hanging from ISim Simulator in the lower frame entitled Processes as shown in fig. 8. If there are no errors the ISim simulator window will pop up and the

9 Computer Structure 9 simulation will be carried out for a short time (usually 1 s). The simulation will stop if a $finish sentence in the testbench file is executed. To see the waveforms click on DEFAULT.WCFG. You can click on the icon to get a full view of the waveforms. Fig. 9 shows the window displaying the waveforms. If you click on the waveforms a yellow will result the corresponding simulation instant and the line values at that instant will be displayed. The notation used for the values of a bus (binary, hexadecimal, decimal..) can be changed by right-clicking on its name and selecting the RADIX option of the floating menu. Figure 9. Simulation of the converter using ISim The frames on the left of the ISim window make it possible to select any signal of any component of the design and add then to the simulation view. We can then display their waveforms, but this requires to relaunch the simulation again. In the top there are several icons to zoom in and zoom out on the chronogram. There are also green icons to navigate along the waveforms. For example, Previous Transition and Next Transition will led us to the previous/next edge of the selected signal. The blue icons are used to control the simulation process with the following actions: clean up the current simulation and go back to simulation zero ( Restart), continue the simulation till finish it ( Run All), continue for a selected time and stop ( Run), execute the Verilog testbench step by step ( Step) and stop the simulation ( Break).