A Flexible SystemC Simulator for Multiprocessor Systemson-Chip
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1 A Flexible SystemC Simulator for Multiprocessor Systemson-Chip Luca Benini Davide Bertozzi Francesco Menichelli Mauro Olivieri DEIS - Università di Bologna DEIS - Università di Bologna DIE - Università di Roma La Sapienza DIE - Università di Roma La Sapienza
2 Summary Introduction Design concept Overview of the bus System architecture Processing unit AHB bus and interfaces Simulation Bus contention and test applications Signal tracing Conclusions and future works
3 Introduction Project description: A SystemC shared memory multiprocessor simulator composed by multiple instruction level models of cached ARM cores connected to a bus supporting multiple master arbitration. Shared memory ARM core Bus Controller ARM core
4 Introduction Design basics - SystemC library - SWARM simulator (C++ class): - - Multiple master bus () SystemC implementation - RedHat Linux 7.2 and gcc UClinux single processor kernel - gcc ARM cross-compiler Why SystemC based design? - re-use of C/C++ code - modularity - standard interface between modules (SystemC)
5 Outlines of the bus (Advanced Microcontroller Bus Architecture) is an on-chip communication standard for high-performance embedded microcontroller supporting multiple units able to initiate read and write operations (bus masters) - AHB: high performance, high clock frequency system modules - APB: low power peripherals Figure: AHB and APB in a typical system.
6 System architecture Overview master device #1 master device #2 master device # AHB multimaster unit slave device #1 slave device #2 slave device # Full SystemC AHB bus implementation - clycle accurate bus transactions - internal multiplexers support up to seven bus masters (ampliable) - internal arbiter resolve bus contention through round robin policy SystemC modules (masters and slaves) - complete SystemC description (lower abstraction level) - encapsulation of C/C++ code (higher abstraction level) Can coexist in the same simulation environment
7 System architecture Processing module ARM7 core Interrupt Controller Local Bus Instruction and Data Cache AHB I/F (SystemC) SystemC signals Timer C++ class SystemC module (wrapper) UART C++ class properties and methods Processing module (master) - include CPU, cache memory and peripherals (C++ class derived from open source SWARM simulator) - a wrapper realizes the interface and synchronization layer between the instruction simulator and the SystemC simulation framework
8 System architecture AHB BUS modules Address and control mux mast address hwdata hreq hrdata hgrant hready AHB I/F master module mast[ ] haddr hmaster ctrl_sign address[ ] Write data mux mast[ ] hwdataout hmaster hwdata[ ] selector Read data mux hsel[ ] hrdata hready readdata[ ] hreq[ ] hready hgrant[ ] selector hmaster ctrl_sign arbiter haddr hsel[ ] decoder haddr hwdataout hsel hmaster ctrl_sign readdata ready AHB I/F slave module AHB mux - arbiter decoder module
9 System architecture Test configuration ARM7 core Interrupt Controller Timer Local Bus Instruction and Data Cache UART AHB I/F Arbiter AHB I/F Memory C++ class SystemC module (wrapper) MASTER #1 SLAVE #1 ARM7 core Interrupt Controller Timer Local Bus Instruction and Data Cache UART AHB I/F AHB I/F Memory C++ class SystemC module (wrapper) MASTER #2 Decoder AHB SLAVE #2 Shared memory dual processor dual memory system
10 Modules declaration and connection //instantiation of the first processing module armsystem soc0("arm_system0"); soc0.clock(clock); soc0.pinoutdef(armmaster[0]); soc0.readymaster(readymast[0]); soc0.requestmaster(requestmast[0]); soc0.burst_ready(burstready[0]); //instantiation of the second processing module armsystem soc1("arm_system1"); soc1.clock(clock); soc1.pinoutdef(armmaster[1]); soc1.readymaster(readymast[1]); soc1.requestmaster(requestmast[1]); soc1.burst_ready(burstready[1]); Master modules declaration: Two identical modules are instantiated and connected to the interface //instantiation of the first memory module ram Memory0("RAM_Memory0"); Memory.clock(clock); Memory.rampin(memoryslave[0]); Memory.readymem(readyram[0]); Memory.requestmem(requestram[0]); //instantiation of the second memory module ram Memory1("RAM_Memory1"); Memory1.clock(clock); Memory1.rampin(sott2ram); Memory1.readymem(sottfwdready); Memory1.requestmem(sottdlyrequest); Slave memory modules: Two identical modules are instantiated and connected to the interface
11 Simulator Test Processing units and bus contentions Screen capture of our dual processor simulator booting multiple parallel UClinux kernels. The two CPU work independently, contending the bus for memory access.
12 Simulator Test Parallel Matrix Multiplication Application: Shared memory matrix multiplication executed by two parallel algorithm running on separate processors Collateral developing activities and tests: - Manual binding at compilation time of program functions to each processor - Dual processor startup and initialization code - Dual processor linker script
13 Simulation - burst access timings example Through SystemC tracing capabilities, cycle accurate signal activity can be visualized
14 Conclusion and Future Works We have implemented a multiprocessor simulation environment in SystemC 1.0, containing an bus model, along with masters (CPUs) and slaves (memories) SystemC modules. The bus model itself is composed by several SystemC modules (arbiter, decoders, multiplexers). master devices (processors) are represented by instruction-level models of cached ARM cores. Characteristics - Easily scalable through multiple instantiation of modules - Easily expandable through new modules implementation - Standard and well defined interface for modules interoperability Future works - Multiprocessor operating system, currently under development (RTEMS) - Expansion of the simulator with new master and slave modules
15 System Architecture Future Expansions CPU (master #1) Memory (slave #1) CPU (master #2) CPU (master #3) AHB BUS Memory (slave #2) I/O (slave #3) DMA controller (master #4) AHB/APB bridge (slave #4)
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