CS 250 VLSI Design Lecture 11 Design Verification
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3 CS 250 VLSI Design Lecture 11 Design Verification John Wawrzynek Jonathan Bachrach Krste Asanović John Lazzaro TA: Rimas Avizienis www-inst.eecs.berkeley.edu/~cs250/
4 IBM Power Million Transistors A complex design... First silicon booted AIX & Linux, on a 16-die system. 96% of all bugs were caught before first tape-out. How???
5 Three main components... (1) Specify chip behavior at the RTL level, and comprehensively simulate it. (3) Technology layer: do the the electrons implement the RTL, at speed and power? (2) Use formal verification to show equivalence between VHDL RTL and circuit schematic RTL. Today, we focus on (1).
6 But our project isn t a CPU! Camera input frames dx/dt dy/dt Hardwired Optic Flow Algorithm Large SRAMs for image data, etc. Input movie streams == CPU test programs Both are history-dependent. Both exercise a small fraction of state space.
7 Today: Processor Design Verification Making a test plan Unit techniques State machine How to write test programs
8 Lecture Focus: Functional Design Test Not manufacturing tests... goal The design correctly executes programs written in the Instruction Set Architecture Correct == meets the Architect s Contract Intel XScale ARM Pipeline, IEEE Journal of Solid State Circuits, 36:11, November 2001
9 Architect s Contract with the Programmer To the program, it appears that instructions execute in the correct order defined by the ISA. As each instruction completes, the architected machine state appears to the program to obey the ISA. What the machine actually does is up to the hardware designers, as long as the contract is kept. Also: The data sheet contract with board or SOC designer.
10 When programmer s contract is broken... Testing our financial trading system, we found a case where our software would get a bad calculation. Once a week or so. Eventually, the problem turned out to be a failure in a CPU cache line refresh. This was a hardware design fault in the PC. The test suite included running for two weeks at maximum update rate without error, so this bug was found. Eric Ulevik
11 A 475M$ Bug
12 Three models (at least) to cross-check. The contract specification The answer (correct, we hope). Simulates the ISA model in C. Fast. Better: two models coded independently. The Chisel RTL model Logical semantics of the Chisel model we will use to create gates. Runs on a software simulator or FPGA hardware. Chip-level schematic RTL Catch synthesis bugs. Formally verify netlist against Chisel RTL. Also used for timing and power. Where do bugs come from?
13 Where bugs come from (a partial list)... The contract is wrong. You understand the contract, create a design that correctly implements it, write correct Chisel for the design... The contract is misread. Your design is a correct implementation of what you think the contract means... but you misunderstand the contract. Conceptual error in design. You understand the contract, but devise an incorrect implementation of it... Chisel coding errors. You express your correct design idea in Chisel.. with incorrect Chisel semantics. Also: CAD-related errors. Example: Chisel-to-Verilog translation errors.
14 For your project: X dx/dt Do bit-by-bit compare of output movie from contract and Chisel. dy/dt y
15 Optic Flow Contract
16 Computing Specify all details of fixed-point arithmetic, so that bit-accurate hardware is efficient. y x t
17 Computing Be sure to specify what happens in the first frame (i.e. what happens on reset) y x t
18 (2) How to do optimization... Think carefully about commutativity, associativity, overflow and underflow, pros and cons of saturating arithmetic, etc. Reminder: All of your implementations need to be bit-accurate with your contract model... so define it carefully!
19 Four Types of Testing
20 Big Bang: Complete Processor Testing Top-down complete how it works Assemble the complete. Execute test program suite on the. Bottom-up Check results. Checks contract model against Chisel RTL. Test suite runs the gamut from 1-line programs to boot the OS.
21 Methodical Approach: Unit Testing Top-down complete unit how it works Remove a block from the design. Test it in isolation against specification. Bottom-up Requires writing a bug-free contract model for the unit.
22 Climbing the Hierarchy: Multi-unit Testing Top-down complete multi-unit unit how it works Remove connected blocks from design. Test in isolation against specification. Bottom-up Choice of partition determines if test is eye-opening or a waste of time
23 Processor Testing with Self-Checking Units Top-down how it works complete with self-checks multi-unit unit Bottom-up Add self-checking to units Perform complete Self-checks are unit tests built into CPU, that generate the right answer on the fly. Slower to simulate.
24 Testing: Verification vs. Diagnostics Top-down complete with self-checks multi-unit unit Bottom-up Verification: A yes/no answer to the question Does the have one more bug? Diagnostics: Clues to help find and fix the bug. Diagnosis of bugs found during complete is hard...
25 CPU program diagnosis is tricky... Observation: On a buggy CPU model, the correctness of every executed instruction is suspect. Consequence: One needs to verify the correctness of instructions that surround the suspected buggy instruction. Depends on: (1) number of instructions in flight in the machine, and (2) lifetime of non-architected state (may be indefinite ).
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27 State observability and controllability Top-down complete with self-checks multi-unit unit Bottom-up Observability: Does my model expose the state I need to diagnose the bug? Controllability: Does my model support changing the state value I need to change to diagnose the bug? Support!= yes, just rewrite the model code!
28 Writing a Test Plan
29 The timeline... Top-down complete Plan in advance what tests to do when... Epoch 1 Epoch 2 Epoch 3 Epoch 4 with self-checks multi-unit Time unit Bottom-up assembly complete correctly executes single instructions correctly executes short programs
30 An example test plan... Top-down complete with self-checks multi-unit Epoch 1 Epoch 2 Epoch 3 Epoch 4 unit early multi unit later with self-checks multi-unit unit diagnostics with self-checks multi-unit unit diagnostics complete verification with self-checks diagnostics unit Bottom-up assembly complete correctly executes single instructions correctly executes short programs Time
31 Unit Testing
32 Combinational Unit Testing: 3-bit Adder Cin Number of input bits? 7 A Sum Total number of possible input values? 2 7 = 128 B 3 Just test them all... Cout Apply test vectors 0,1, to inputs. 100% input space coverage Exhaustive
33 Combinational Unit Testing: 32-bit Adder Cin Number of input bits? 65 A Sum Total number of possible input values? 2 65 = 3.689e+19 B 32 Cout Just test them all? Exhaustive does not scale. Combinatorial explosion!
34 Test Approach 1: Random Vectors Cin how it works A B Sum Apply random A, B, Cin to adder. Check Sum, Cout. Cout When to stop? Bug curve. Bug Rate Bugs found per minute of Time
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36 Test Approach 2: Directed Vectors A B Cin + Directed random Sum how it works Hand-craft test vectors to cover corner cases A == B == Cin == 0 Cout Black-box : Corner cases based on functional properties. Clear-box : Corner cases based on unit internal structure.
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39 State Machine Testing CPU design examples DRAM controller state machines Cache control state machines Branch prediction state machines
40 Testing State Machines: Break Feedback Rst Change Next State Combinational Logic D Q R D Q G D Q Y Isolate Next State logic. Test as a combinational unit. Easier with certain HDL coding styles...
41 Testing State Machines: Arc Coverage Rst == 1 Change == 1 R Y G R Y G Change == Change == 1 R Y G Force machine into each state. Test behavior of each arc. Intractable for state machines with high edge density...
42 Regression Testing Or, how to find the last bug...
43 Writing complete CPU test programs Top-down complete with self-checks Single instructions with directed-random field values. Epoch 1 Epoch 2 Epoch 3 Epoch 4 with self-checks White-box Instructions-inflight sized programs that stress design. with self-checks complete multi-unit Time unit Bottom-up assembly complete correctly executes single instructions correctly executes short programs Tests that stress long-lived non-architected state. Regression : re-run subsets of the test library, and then the entire library, after a fix.
44 Formal Verification: How does it work? Cadence Labs + EECS Adjunct Prof. Verity - a Formal Verification Program for Custom CMOS Circuits Andreas Kuehlmann Arvind Srinivasan David P. LaPotin Boolean Equivalence Checking. How can you show two RTL descriptions are equivalent using static techniques? We begin by formally defining the problem...
45 The formal problem statement... Verilog RTL State Machine C A : Combinational logic. S A : Flip-flops. Question: If we initialize flip-flops appropriately... x x A FSM A C A y A z A z A S A Clk Reset A brief sketch of how the tool goes about answering the question... c For any sequence of input vectors Xo, X1,... C B : Combinational logic. S B : Flip-flops. Schematic State Machine B x FSM B z B C B S B Clk Reset z B B y Will C ever be 1? If no, the Verilog and schematic RTLs are Booleanequivalent.
46 FSM Equivalence: A two-step algorithm (1) Flip-flop equivalence. We assume we can find all flip-flops in RTL for each FSM. If the FSMs do not have the same number of flip-flops, FSMs not EQ. x x A FSM A C A y A z A z A S A Clk Reset (2) Prove C A = C B. Like proving DeMorgan s theorem for a homework assignment... an exercise in symbolic manipulation. c Otherwise, run an algorithm to reorder S A (and thus C A ) to match S B. Trivial solution: the user names the flip-flops. But modern tools can do it automatically. B x FSM B z B C B S B Clk Reset z B B y But the symbols are manipulated by a computer program... and the functions are very large! Rocket science would start here...
47 Conclusion -- Testing Processors" Bottom-up test for diagnosis, top-down test for verification. Unit : avoiding combinatorial explosions. Complete CPU tests: write programs that stress the hard parts of the design. Make your plan early! After the break: Chisel tips.
48 Next Week: Transition to Project Mode
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