18. Synopsys Formality Support

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1 18. Synopsys Formality Support QII Introduction Formal verification of FPGA designs is gaining momentum as multi-million System-on-a-Chip (SoC) designs are targeted at FPGAs. Use the Formality software to easily verify logic equivalency between the RTL and DC FPGA post-synthesis netlist, and between the DC FPGA post-synthesis netlist and Quartus II post-place-and-route netlist. Beginning with version 4.2, the Quartus II software interfaces with EDA tools including the Formality and DC FPGA software from Synopsys. This chapter discusses the following: Formal Verification Formal Verification Support on page 18 2 Generating Post-Synthesis Netlist for Formal Verification on page 18 3 Generating the VO File and Formality Script on page 18 4 Quartus II Scripts for Formality on page Comparing Designs Using the Formality Software on page Known Issues and Limitations on page Formal Verification Formal verification uses exhaustive mathematical techniques to verify design functionality. There are two types of formal verification: equivalence checking and model checking. This section discusses equivalence checking. Equivalence Checking Equivalence checking compares the logical equivalence between the original design and the modified or revised design using mathematical techniques. This method reduces the verification time several-fold compared to the traditional method of performing verification using test vectors. Using a formal verification methodology provides the following key advantages: Faster time-to-market No testbenches or test vectors Results in hours compared to days using traditional verification methods Altera Corporation 18 1

2 Quartus II Handbook, Volume 3 Formal Verification Support The Quartus II software supports formal verification using the Formality software for the DC FPGA Synthesis tool as shown in Figure Figure Equivalence Checking in the FPGA Design Flow RTL DC FPGA Synthesized Netlist Equivalence Checking/ Formality Quartus II Post-Placeand-Route EDA Tools and Device Support The formal verification flow using the Quartus II software and Synopsys Formality software requires the following software versions: Quartus II software, beginning with version 4.2 Synopsys DC FPGA software, beginning with version W _EA1 Synopsys Formality software, beginning with version The formal verification flow, using the Quartus II and Synopsys Formality software, supports Solaris and Linux platforms, and supports Stratix series devices. Formal Verification Between RTL and Post-Synthesis Netlist The first step in the FPGA design flow is to synthesize the RTL code using the DC FPGA to generate the synthesized verilog netlist. Equivalence checking using formal verification is performed between the RTL and the synthesized netlist to make sure the synthesis tool has not altered the original functionality of the design Altera Corporation Preliminary

3 Generating Post-Synthesis Netlist for Formal Verification 1 For more information on how to use the DC FPGA software for synthesizing Altera device designs, refer to the Synopsys Design Compiler FPGA Support chapter in volume 1 of the Quartus II Handbook. Generating Post-Synthesis Netlist for Formal Verification During the synthesis process, the DC FPGA synthesis tool performs operations such as: Modifying the net/instance names Register duplication State machine extraction by different methods Changes caused by these synthesis operations cause comparison point matching issues and false verification failures. In order to make sure that the Formality software is aware of the design transformations performed during the synthesis, the DC FPGA software writes out a Synopsys setup verification file (.svf) to be read into the Formality software. To ensure the SVF constraint file contains all the formal verification setup constraints, you need to set certain commands in the DC FPGA software before compiling the design as detailed in the following section. DC FPGA Software Settings The Formality software does not support the register merging or register retiming synthesis operations, which are off by default, but it is necessary to verify that these settings are turned off during synthesis. Some of the commands necessary to turn off these options and generate a valid Verilog netlist for the formal verification purpose are described in this section. 1 For more information on creating the Tcl script file to perform synthesis, refer to the DC FPGA User Guide or the Synopsys Design Compiler FPGA Support chapter in volume 1 of the Quartus II Handbook. To set most of the required synthesis settings to generate a valid formal verification netlist, use the following command: set_fpga_defaults -formality <architecture_name> For example: set_fpga_defaults -formality altera_stratix Altera Corporation 18 3 Preliminary

4 Quartus II Handbook, Volume 3 To view all of the settings performed by this command, add -verbose to this command. In addition, you will need to execute the additional commands shown in Table Table Commands and Affect of Each Command Command set verilogout_write_constant_nets true change_names -rule verilog -hierarchy set_verification_friendly_mode -filename \ <top_level>.svf -append -allow_override write -hier -f verilog -o $outputdir/<top_level>.v Affect Add this command at the beginning of the script to allow unconnected nets to be driven by either power or ground. This command must be added after the compile command to set the Verilog naming rule to the output netlist for all levels of hierarchy. This command helps DC_FPGA to write out a SVF constraint file to be read into the Formality software. This command writes out a Verilog netlist for Formal Verification. For a sample DC FPGA script that is ready for compilation, refer to Tcl Sample Script on page Post synthesis Verilog netlist for formal verification can be generated by executing the Tcl script either in fpga_vision (GUI) or fpga_shell-t (command line). 1 For comparing RTL against post-synthesis netlist using the Formality software, refer to the DC FPGA Software User Guide. Generating the VO File and Formality Script The following steps describe how to set up the Quartus II software environment to generate the place-and-route, post-place-and-route VO netlist file, and Formality script compatible for formal verification. 1. Create a new Quartus II project or open an existing project. 2. On the Assignments menu, click Settings. The Settings dialog box is shown. 3. In the Category list, select Files. The Files page is shown. 4. Highlight the input file by clicking on it, then click Properties and select Verilog Quartus Mapping File. Click OK Altera Corporation Preliminary

5 Generating the VO File and Formality Script 5. In the Category list, select Design entry/synthesis under EDA Tool Settings. 6. In the Tool name list, select Design Compiler FPGA (Figure 18 2). These settings can also be performed using the following Tcl commands: set_global_assignment -name VQM_FILE <verilog_file_from_dc_fpga> set_global_assignment -name \ EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Design Compiler FPGA" set_global_assignment -name EDA_LMF_FILE \ dc_fpga.lmf -section_id eda_design_synthesis Figure EDA Tools Selection Altera Corporation 18 5 Preliminary

6 Quartus II Handbook, Volume 3 7. In the Category list, select Formal verification. In the Tool name list, select Formality (Figure 18 3). Figure EDA Tools Selection 8. Click OK. 9. From the Assignments menu, click Settings. The Settings dialog box is shown. 10. In the Category list, click the + icon to expand Analysis and Synthesis Settings and select Synthesis Netlist Optimizations. The Synthesis Netlist Optimizations page is shown Altera Corporation Preliminary

7 Generating the VO File and Formality Script 11. Turn off the Perform gate-level register retiming option (Figure 18 4). Figure Synthesis Netlist Optimizations 12. In the Category list, click the + icon to expand Fitter Settings and select Physical Synthesis Optimizations. The Physical Synthesis Optimizations page is shown. Altera Corporation 18 7 Preliminary

8 Quartus II Handbook, Volume Turn off the Perform register retiming option (Figure 18 5). Figure Setting Parameters for Netlist Optimizations Performing register retiming on a design usually results in moving and merging/duplicating registers along the critical path. Because equivalence checkers compare the cones of logic terminating at registers, you should not move or duplicate the registers during optimization by the Quartus II software. If the options in this section are not selected, the Formality software script could be presented with a different set of compare points, and the resulting netlist is difficult to compare against the reference netlist file. The Quartus II software, beginning with version 4.2, supports register duplication to improve the timing by duplicating the logic Altera Corporation Preliminary

9 Generating the VO File and Formality Script f To learn more about register duplication, refer to the Analyzing and Optimizing the Design Floorplan chapter in volume 2 of the Quartus II Handbook. 14. Perform a full compilation of the design either on the Processing menu by clicking Start Compilation or by clicking on the start compilation arrow icon located in the tool bar. Handling Black Boxes Every design entity in the golden netlist must have a corresponding formal verification model in order to successfully run formal verification. Design entities in the golden netlist without a corresponding formal verification model are handled as black boxes whose boundary interfaces must be preserved. These design entities appear in the netlist if one of the following situations apply: Altera megafunctions including library of parameterized modules (LPM s) 1 The black-box property is only applied to LPM modules that do not have a formal verification model. Encrypted intellectual property (IP) cores Entities that are defined in the design format other than Verilog HDL or VHDL The Quartus II software has the capability of automatically identifying the black boxes and sets the property Preserve Hierarchical Boundary to Firm to preserve the boundary interfaces of the black boxes which helps the formal verification. You can also specify the black box property on entities that should be compared by the Formality software. To do this make the following assignments either using Tcl commands or GUI for the entities in question: Tcl Command The following two commands preserves the boundary interface of the entity: dram. set_instance_assignment -name\ PRESERVE_HIERARCHICAL_BOUNDARY FIRM -to -entity dram set_instance_assignment -name EDA_FV_HIERARCHY\ BLACKBOX -to -entity dram Altera Corporation 18 9 Preliminary

10 Quartus II Handbook, Volume 3 GUI Preserving the boundary interface of an entity using GUI. Assign the EDA Formal Verification Hierarchy value as blackbox. Assign the Preserve Hierarchical Boundary assignment with a value of Firm to the entity (Figure 18 6). Figure Making a Black Box Assignment to an Entity The Quartus II software compiler generates the following files and directories: VO file: <design_name>.vo. Script file: <design_name>.fms used with Formality software. A black-box directory: black boxes that contains all the user defined black-box entities in the design which is located in the following directory: /<project directory>/fv/formality/blackboxes. The script file contains the setup constraints used along with the Formality software. The <entity>.v file in the black-boxes directory contains the module description of only those entities that are not defined in the formal verification library. For a sample script containing the setup commands generated by the Quartus II software, refer to Tcl Sample Script on page Altera Corporation Preliminary

11 Quartus II Scripts for Formality Quartus II Scripts for Formality The Quartus II software generates scripts to use with the Formality software. This section describes the Formality software commands used within the scripts to help customers comparing the implementation and reference netlists. Table 18 2 describes the Formality software commands within Quartus II generated scripts. Table Formality Software Commands within Quartus II Generated Scripts Command read_verilog <design files> set_compare_rule <rule> set signature_analysis_matching <value> set_constant <value> set hdlin_altera_generate_naming <value> Set_user_match <mapping_point_name> Affect This command reads both the reference and implementation netlists in addition to the appropriate library models. Adds a name matching rule that Formality software applies to a design before creating compare points. Use this command to specify whether or not to use signature analysis to match previously compared points. This command allows you to set the logic state of a design object to either 0 or 1. This command directs Formality software to apply alter naming conventions for registers. Use this command to create pairs of matched points to compare those that Formality software could not match during its matching process. Comparing Designs Using the Formality Software To verify the functional equivalence between post-synthesis and post-place-and-route netlists, use the script file <file_name>.fms since it contains references to the macros defined in the Altera formal verification library. Some of the macros used are: _ALTERA_FAMILY_IS_STRATIX_ POST_FIT FORMALITY GATES_TO_GATES An example on the use of these macros is shown in the read_verilog command in the previous section. This script file <file_name>.fms is executed from either the GUI or using the following command: %formality -file <file_name>.fms f For more information about using the Formality software, refer to the Formality User Guide. Altera Corporation Preliminary

12 Quartus II Handbook, Volume 3 1 The Formality software does not support inferred RAMs in RTL while performing RTL-to-Gates verification. Therefore, you should apply the black box property to RAM that is instantiated by the RTL code. Known Issues and Limitations This section discusses known issues and limitations of the formal verification flow using the DC FPGA, Quartus II, and Formality software: 1. Formal verification of post synthesis verses post-place-and-route netlist does not support latches because latches are implemented using combinational logic with a feedback loop which poses a problem to the Formality software. 2. If an LPM or an Altera megafunction module is inferred and all the ports of the module are not used, then unused ports should be connected to default values in the post-synthesis Verilog HDL netlist. 3. The Quartus II software may optimize away logic feeding a black box, resulting in mismatches on the blackbox inputs. For example, if certain bits of a RAM output are not being used, then the Quartus II software optimizes away the logic feeding the corresponding data inputs. Conclusion Related Links Formal verification enables verification of the design during all stages from RTL to place-and-route. As designs become larger, design verification using traditional methods becomes too time consuming. Thus, formal verification easily verifies that any modifications to the netlist in the physical domain have not altered from the Golden netlist. Advanced debugging capabilities within Formality software pinpoints the source of the differences between the Reference and Implementation netlists, enabling the user to easily fix the differences. Altera website: About Using the DC FPGA Software with the Quartus II Software Altera Corporation Preliminary

13 Tcl Sample Script Tcl Sample Script This section provides an example of the DC FPGA software script to perform synthesis and an example formal verification script generated by the Quartus II software. DC FPGA Synthesis Script The following example script presents the Altera recommended settings in the DC FPGA software for synthesizing the design for the Stratix architecture. The script also generates the Verilog netlist file for formal verification using the Formality software. These tasks are performed in the following five sections of the script: Setting up the library Default synthesis settings for Altera Stratix Analyzing the design files Compiling the design Generating the Verilog netlist for formal verification # Setup file for Altera Stratix Devices # Tcl style setup file but will work for # original DC shell as well # Need to define the root location of the # libraries by changing # the variable $dcfpga_lib_path set dcfpga_lib_path "<dcfpga_rootdir>\ /libraries/fpga/altera" set search_path ". $dcfpga_lib_path $dcfpga_lib_path/stratix $search_path" set target_library "stratix.db" set synthetic_library "tmg.sldb altera_mf.sldb\ lpm.sldb" set link_library "* stratix.db tmg.sldb\ altera_mf.sldb\ lpm.sldb" set cache_dir_chmod_octal "1777" set hdlin_enable_vpp "true" set post_compile_cost_check "false" set_fpga_defaults -formality altera_stratix set formality_altera_debug true set_verification_friendly_mode -filename <top_level>.svf -append \ -allow_override set verilogout_no_tri true set verilogout_write_constant_nets true set compile_fix_multiple_port_nets true ## Setup design directory for database, temporary files # and netlist #</OUTPUTDIR># set outputdir <directory_name> file mkdir $outputdir/work define_design_lib WORK -path $outputdir/work Altera Corporation Preliminary

14 Quartus II Handbook, Volume 3 ## Setup the Top-level design name set top <top_level_module> ##Setup synthesis optimization options set dcfsm_force_encoding neutral #<READFILES># ##Analyze source files ##Elaborate design elaborate $top #</ELABORATE># ##Specify Target device current_design $top set_fpga_target_device AUTOFASTEST ## Insert pad during synthesis set_port_is_pad [get_ports "*"] #<FPGACONST># ## Specify clock constraints #</FPGACONST># #<COMPILE># ##Setup compile options ungroup -small 500 ## Compile design compile change_names -rule verilog -hierarchy #<REPORT># ##Generate netlist/reports/constraints for PAR write -hier -f verilog -o $outputdir/$top.v report_fpga > $outputdir/fpga.rpt Quartus II Software-Generated Formal Verification Script The following example script shows the sample setup commands generated by Quartus II software: read_verilog -i -vcs \ "+define+_altera_family_is_stratix_ \ +define+post_fit \ +define+formality -y $QUARTUS/eda/fv_lib/verilog \ +libext+.v -y \ /home/formality/testcases/mult/quartus/fv/ \ formality/blackboxes" \ $PROJECT/fv/formality/mult_ram.vo set_top mult_ram set_black_box i:/work/altsyncram report_black_box set_compare_rule i:/work/mult_ram -from "_ai$" -to "" set_compare_rule r:/work/mult_ram -from "\/" -to "_a" set_compare_rule i:/work/mult_ram -from "\/" -to "_a" match verify Altera Corporation Preliminary

15 Referenced Documents Referenced Documents Document Revision History This chapter references the following documents: Formality User Guide Analyzing and Optimizing the Design Floorplan chapter in volume 2 of the Quartus II Handbook Table 18 3 shows the revision history for this chapter. Table Document Revision History Date and Document Version Changes Made Summary of Changes v7.2.0 May 2007 v7.1.0 March 2007 v7.0.0 November 2006 v6.1.0 May 2006 v6.0.0 October 2005 v5.1.0 May 2005 v5.0.0 January 2005 v1.0 Reorganized Referenced Documents on page Added Referenced Documents. Updated Quartus II software 7.0 revision and date only. No other changes made to chapter. Added new revision history table format to the document. Minor updates for the Quartus II software version Updated for the Quartus II software version 5.1. Chapter 15 was previously Chapter 13 in version 5.0. New functionality for Quartus II software 5.0. Initial release. Altera Corporation Preliminary

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