Bibliography. Measuring Software Reuse, Jeffrey S. Poulin, Addison-Wesley, Practical Software Reuse, Donald J. Reifer, Wiley, 1997.

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1 Bibliography Books on software reuse: Measuring Software Reuse, Jeffrey S. Poulin, Addison-Wesley, Practical Software Reuse, Donald J. Reifer, Wiley, Formal specification and verification: the VSPEC homepage. Formal Specification and Verification of Digital Systems, George Milne, McGraw-Hill, Formal Hardware Verification, Thomas Kropf (ed.), Springer, Management processes: 1. a description of the UltraSPARC project, mentioning construct by correction. 2. Winning the New Product Development Battle, Floyd, Levy, Wolfman, IEEE. Books and articles on manufacturing test: 1. Testability on Tap, Colin Maunder et al., IEEE Spectrum, February 1992, pp Aiding Testability also aids Testing, Richard Quinell, EDN, August 12, 1990, pp ASIC Testing Upgraded, Marc Levitt, IEEE Spectrum, May 1992, pp Synopsys Test Compiler User s Guide, v3.3a, Synopsys Test Compiler Reference Manual, v3.2, 1994.

2 286 Reuse Methodology Manual Synopsys Certified Test Vector Formats Reference Manual. Digital Systems Testing and Testable Design, M. Abromovici et al., Computer Science Press, The Boundary Scan Handbook, Kenneth Parker, Kluwer Academic Publishers, The Theory and Practice of Boundary Scan, R. G. Ben Bennetts, IEEE Computer Society Press. Testability Concepts for Digital ICs, Franz Beenker et al., Philips Corp, A Comparison of Defect Models for Fault Location with IDDQ Measurements, Robert Aitken, IEEE Design & Test, June 1995, pp Books and articles on synthesis: 1. Flattening and Structuring: A Look at Optimization Strategies, Synopsys Application Note Version 3.4a, April 1996, pp. 2-1 to VHDL Compiler Reference Manual, Synopsys Documentation Version 3.4a, April 1996, Appendix C. 3. DesignTime Reference Manual, Synopsys Documentation Version 3.4a, April Commands, Attributes, and Variables, Synopsys Documentation Version 3.4a, April 1996.

3 Index Symbols definestatements (Verilog) 98 A active-low signals 83 algorithmic (behavioral) model 19 all_registers 143 application testing 157 architecture (VHDL) 93 arrays 94 ASIC design flow diagram 12 aspect ratio 185 asynchronous design style 33 logic 128 reset 37 ATPG 144 B BIST logic 59,183 RAM 58 block definition 3 system interconnect 50 block constructs (VHDL) 101 blocking assignments (Verilog) 117 boundary scan 184 branch coverage 174 bug tracking 267 bus functional model 195 buses naming convention 83 on-chip 50, 97 tristate 97 C case statements 120 check_design 143 check_test 144 clock buffers 40, 103 coding guidelines 101 distribution 40 domains 36 frequencies 36 gating 103, 105 hard macro 184 internal generation 104 mixed edges 102 naming convention 83 synthesis 142 tree 40 code profiling 136 coding guidelines basic 82 clock and reset 101 emulation 261 exceptions 215 functions 93 HDL translation 100 labels 96 loops and arrays 94

4 288 Reuse Methodology Manual memory 135 partitioning 125 portability 97 readability 87 synthesis 108 synthesis scripts 150 combinational blocks 116 feedback 113 logic partitioning 126 loops 143 paths 139 comments, in source files 87 compliance tests 156 condition coverage 175 configuration (VHDL) 93 constant declarations (VHDL) 101 constants 98 construct by correction methodology 15 core 3 corner tests 156 coverage analyzing 174 branch 174 condition 175 macro testbench 174 path 175 statement 174 toggle 176 trigger 176 D data management design archive 268 multi-site 267 revision control 265 datapath design issues 148 design methodologies 148 debug strategy selection 51 structures 51 deliverables hard macro 210 soft macro 208 design archive 213, 268 design for reuse coding guidelines 82 general guidelines 5 requirements 5 design methodology bottom-up 15 spiral model 13 System-on-Chip 11 top-down 15 waterfallmodel 11 design process hard macro 190 System-on-Chip 19 design reuse definition 1 in System-on-Chip designs 2 design reviews 269 DesignWare 99 documentation 78 requirements 214 soft macro 80 E emulation coding guidelines 261 limitations 257 model 198 pros and cons 158 entity (VHDL) 93 equivalence checking 144, 254 executable specification 18 F false paths 132 firm macro 4 floorplanning feedback to synthesis 144 hard macro 39 specification 38 formal specification 18 formal verification 80 hard macro 193 system-level verification 254 FPGA prototype 251 full functional model 198 full scan 183 functional specification 75, 269 G gates, instantiating 100, 133 generate statements (VHDL) 101 GTECH library 100 H hard macro aspect ratio 185 bus functional model 195 clock implementation 184 definition 4

5 Reuse Methodology Manual 289 deliverables 210 design for test 183 design process 190 development issues 179 emulation model 198 floorplanning 39 full functional model 198 hardware model 198 physical design 190 pin placement 187 porosity 186 power distribution 187 productization 190 reset implementation 184 selection 221 verification 193 hard-coded numerics 98, 151 hard-coded paths 151 hardware accelerator 256 hardware model 198 hardware modeler 158 hardware specification 17 hardware/software cosimulation 20, 260 partitioning 20 HDL translation 80, 89, 97 header, in source files 85 I if-then-else statements 120 interconnect on-chip blocks 50 IP definition 3 L labels 96 latches avoiding 110 checking for 143 design issues 33 limited production 173 loops 94 LPGA prototype 251 M macro 3 design process 67, 73 partitioning 75 synthesis strategy 141 timing budget 139 timing constraints 139 manufacturing test on-chip structures 58 strategy selection 57 memory BIST 58 coding guidelines 135 test methodology 58 microprocessor system-level modeling 245 multibit signals 83 multiplexers 120 N namingconventions 82 nonblocking assignments (Verilog) 117 P parameter mapping 92 naming convention 82 partitioning asynchronous logic 128 chip-level 134 combinational logic 126 macro into subblocks 75 path coverage 175 phase-locked loop 36 physical design hard macro 190 of SOC with macros 224 pin placement 187 place-and-route 144 porosity 186 port grouping 90 mapping 92 naming convention 84 ordering 89 power analysis 76 power distribution 187 product development lifecycle 269 productization hard macro 190 soft macro 78 project plan 269 prototype 78, 158, 173 R RAM generators 147, 223 random tests 157 rapid prototyping 172

6 290 Reuse Methodology Manual registers for output signals 125 inferring 109 regression tests 266, 267 report_timing 143 reserved words 89 reset asynchronous 37 coding guidelines 101 conditional 106 hard macro 184 internal generation 106 namingconvention 83 strategy 36 synchronous 37 synthesis 142 resource sharing 128 revision control always-broken model 266 always-working model 266 implementing 265 requirement 78, 150, 213 routing channels 186 S scan insertion 76 sensitivity list 114 sequential blocks 116 set_driving_cell 141 set_load 141 signal naming convention 84 registering outputs 125 signal assignments (VHDL) 119 silicon prototype 252 simulation code profiling 136 gate-level 80,177 simulator compatibility 97 macro portability 80 soft macro definition 4 deliverables 208 designing with 223 documentation 80 formal verification 80 gate-level simulation 80 installation 222 productization 78 selection 222 synthesis challenges 137 verification challenges 153 software specification 18 specification block 21 executable 18 formal 18 functional 75, 269 hardware 17 importance of 17 requirements 17 software 18 subblock 75 system 19 technical 75 spiral model 13 statement coverage 174 static timing analysis 177 std_logic 97 std_logic_vector 97 std_ulogic 97 std_ulogic_vector 97 subblock definition 4 specification 75 synthesis strategy 141 technical specification 75 timing budget 139 timing constraints 139 subtypes (VHDL) 97 synchronous design style 33 memory interface 135 reset 37 synthesis clock network 142 code checking after 143 code checking before 143 coding guidelines 108 early in design 140 guidelines 138 partitioning for 125 reset network 142 strategy selection 39, 138 top-level macro 76 synthesis scripts embedded 99 guidelines 150 system verification application-based verification 244 emulation 251 fast prototyping 249 formal verification 254 gate-level verification 253 hardware/software cosimulation 260

7 Reuse Methodology Manual 291 in-circuit testing 260 RTL acceleration 259 specialized hardware 256 strategy 240 test plan 240 verifying behavior and data 242 verifying macro interfaces 241 verifying macro transactions 241 System-on-Chip design challenges 2 design flow diagram 14 design methodology 11 verification. See system verification system-level. See system verification timing 177 tools 157 virtual component 4 VITAL 84 VSIA 4 VSPEC 18 W waterfall model 11 wire load models 142 T technical specification 75 technology independence 97 macro portability 80 test insertion 76 testability checking for 144 coding for 108 gated clocks 103 testbench output checking 162 stimulus generation 162 timing budget macro 139 subblock 139 timing constraints macro 139 subblock 139 timing verification 177 toggle coverage 176 translation, HDL 80 trigger coverage 176 types (VHDL) 97 U user guide 214 V variable assignments (VHDL) 119 verification application testing 157 compliance tests 156 corner tests 156 hard macro 193 macro 153 plan 155 random tests 157 strategy selection 41, 156