Tutorial 2.(b) : Synthesizing your design using the Synopsys Design Compiler ( For DFT Flow)
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1 Tutorial 2.(b) : Synthesizing your design using the Synopsys Design Compiler ( For DFT Flow) Objectives: In this tutorial you will learrn to use Synopsys Design Compiler (DC) to perform hardware synthesis using the xlite_core standard library. You will use Synopsys Design Compiler to elaborate Register Transfer Level description of a design coded in Verilog, set optimization constraints, synthesize to gates, and prepare various area and timing reports. 1. Introduction: What is Synthesis? Process of converting a high-level description of the design into an optimized gate-level representation given a standard-cell library and certain design constraints. Standard Library or Technology Library (the one used here is xlite_core.db) - It can have basic logic gates (cells) like and, or etc. It can have macro cells like adders, muxes and flip flops A standard cell library format used for Design Compiler is.db (for example xlite_core.db). A cell library is available in.lib format (xlite_core.lib) which is compiled by Library Compiler (part of DC package) to generate a.db format library. For details on how to generate standard cell library refer to Design Compiler user guide. Design Compiler as Synthesis Tool: A synthesis tool like Design Compiler (DC) takes an RTL hardware description and a standard cell library as input and produces a gate-level netlist as output. The resulting gate-level netlist is a completely structural description with only standard cells at the leaves of the design. Internally, a synthesis tool performs many steps including high-level RTL optimizations, RTL to unoptimized boolean logic, technology independent optimizations, and finally technology mapping to the available standard cells. 2. Invoking Design Vision : Type the following at the terminal from your home directory(this brings design compiler HOME to the PATH variable) cp ~CadTools/bashrc_files/bashrc_all.bashrc Close the terminal and re-fire the terminal again. All commands for Design Compiler can now be run from your user account.
![Type design_vision from your project folder to invoke GUI version of design compiler [bibhasghoshal@localhost s27]$ design_vision A GUI opens up 3.](/docs-images/77/76594615/images/2-0.jpg "Preparation: The Design Compiler is prepared to locate the design libraries to be used (in this case xlite_core.db). This is done by setting some environment variables for Design Compiler(DC).")
2 Type design_vision from your project folder to invoke GUI version of design compiler s27]$ design_vision A GUI opens up 3. Preparation: The Design Compiler is prepared to locate the design libraries to be used (in this case xlite_core.db). This is done by setting some environment variables for Design Compiler(DC). The commands for setting up environment variables for locating design libraries are: set search_path {./libs/library} /* instructs DC to search for the target library at this path */ set target_library {"xlite_core.db"} /* the name of the target design library used for synthesis */ set link_library {"xlite_core.db"} /* same as the target library */ set symbol_libary { xlite_core.sdb } /* library having symbols of gates in xlite_core library */
3 These commands can be invoked by either of the following ways: (i) type the commands at the command line of the Design Vision window(have to do it for each new project). (ii) write the commands in a file. Save it in the project folder by the name synopsys_dc.setup and execute the set up script by File -> Execute Script from the Design Vision window. This is a one time process and is strongly recommended Meaning of the commands set search_path {./libs/library} /* instructs DC to search for the target library at this path */
4 set target_library {"xlite_core.db"} /* the name of the target design library */ set link_library {"xlite_core.db"} /* same as the target library */
5 set symbol_library {"xlite_core.sdb"} 4. Analyzing and Elaborating your Design At the GUI, File-> Read (Read your source file s27.v from the src folder). This loads your verilog design into Design Compiler.
6 After the source file is read make sure, the correct library is loaded as link library(at the transcript window, the following statement should occur: Loading Link library xlite_core 5. Compile your design
7 At the GUI, design-> Complile design-> OK 6. Check the synthesized netlist. View the schematic view (Schematic->New Design Schematic View) and check whether the gates in the current design are gates of xlite_core library.
8 7. Saving the netlist Save your netlist in verilog format and save it in syn folder (In the tutorial the netlist is saved as s27_syn.v)
9 8. Report Area and Power: At the GUI, generate reports of your synthesized design by the following i. Report Area ii. Report Power Save the reports generated as text files in a report folder in the project folder s27. References: 1. Advanced ASIC Chip Synthesis Using Synopsys Design Compiler Physical Compiler and PrimeTime by Himanshu Bhatnagar, ISBN-10: ISBN-13: Publication Date: December 1, 2001 Edition: 2nd 2. Design Compiler User Guide
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