Reading the Design into PT

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1 Reading the Design into PT Learning Objectives Given a set of design and library files, you will read them into PrimeTime memory and access the design objects. After completing this lab, you should be able to : set the search_path and link_path variables correctly read a top-level Verilog/VHDL netlist and link using Verilog/VHDL sub blocks and the library read a top-level Verilog/VHDL netlist and link using DB sub blocks and the library read a complete netlist in VHDL/Verilog/DB and library, link efficiently and access sevaral objects within the design 45 minutes UNIT Unit 3 Reading the Design into PrimeTime 3-1 Synopsys S36

2 Getting Started Directory structure and relevant files../libs/ Directory with Library files core_slow.db Cell library for setup check Lab3_Read/ Directory to perform this lab.synopsys_pt.setup PrimeTime Setup Scripts/ Scripts directory task1_solution.pt Partial script for Task1 task2_solution.pt Partial script for Task2 Source/ Verilog/ Verilog design directory RISC_CORE*.v Top-level netlist *.v Sub designs in RISC_CORE DB/ DB design directory RISC_CORE*.db Top-level netlist *.db Sub designs in RISC_CORE If you need help Use the lecture material, SOLD or the Quick Reference Guide. pt_shell> help read* pt_shell> help verbose read_verilog pt_shell> read_verilog help pt_shell> man read_verilog pt_shell> printvar link* pt_shell> echo $link_create_black_boxes pt_shell> man link_create_black_boxes 3-2 Reading design into PrimeTime

3 Reading the Design into PrimeTime Read Top-level design. Link using Verilog sub blocks Read Top-level design. Link using DB sub blocks Read & Link Top-level hierarchical netlist. Access design objects Answer to Lab Review Questions Done Your goals are to: - Read a top-level RISC_CORE design and link using Verilog sub blocks and then using DB sub blocks - Find and fix at least 3 problems - Read hierarchical RISC_CORE netlist and link efficiently and still access all the required design objects Reading design into PrimeTime 3-3

4 Background You are provided with the gate level netlist of the RISC_CORE design, the library and an incomplete.synopsys_pt.setup file. Task 1. Read the Top-level design. Link using Verilog Sub Blocks 1. Make sure that your current directory is./lab3_read; Invoke pt_shell to log the session to a log file. unix% pt_shell tee lab3.log 2. Review the link_path and search_path variables. Do you see any problems?. (You do not need to fix anything in this step.) 3. Read the top-level design netlist of RISC_CORE. pt_shell> read_verilog RISC_CORE.v Question 1. What was the problem?... Question 2. What are the 2 ways you can fix this problem? Update the search_path to point to the Verilog directory and repeat Step-3. pt_shell> lappend search_path./source/verilog 5. Link the current_design. pt_shell> current_design RISC_CORE pt_shell> link_design Question 3. Are there unresolved references?... Question 4. Is the design reported successfully linked? Reading design into PrimeTime

5 6. PT creates black boxes for unresolved references and the link was reported as successful. This will not be helpful for STA. Relink with link_create_black_boxes variable set to false. pt_shell> printvar *black*box* pt_shell> set link_create_black_boxes false pt_shell> link Question 5. How many references are unresolved?... Question 6. Is the design reported successfully linked? There is a LNK-001 error indicating that PT cannot read the link_path file core_slow.db. Fix this problem by updating the search_path variable to include the needed directory as well as the link_path variable to include PT memory. Perform link. pt_shell> printvar link_path pt_shell> set link_path * core_slow.db pt_shell> printvar search_path pt_shell> lappend search_path../libs pt_shell> link Question 7. How many references are unresolved now?... Question 8. Are these library cells or sub blocks unresolved? Although the Verilog sub blocks are present in the search_path, PT cannot automatically read them to resolve the references. You have to read them manually and then link. Reading design into PrimeTime 3-5

6 pt_shell> ls Source/Verilog/* pt_shell> set SUB_LIST ALU \ CONTROL \ DATA_PATH \ INSTRN_LAT \ PRGRM_CNT_TOP \ REG_FILE \ STACK_TOP pt_shell> foreach SUB $SUB_LIST {? read_verilog ${SUB}.v? } pt_shell> link Question 9. Are there any unresolved references?... Question 10. What design has been successfully linked now?... The goal was to link RISC_CORE, but you accidentally linked a sub design. This can happen when reading Verilog/VHDL files. 9. You will now fix this error. Take a note of the Unlinking.. message during link. PT can hold only one linked design in memory at a time. pt_shell> current_design RISC_CORE pt_shell> link Question 11. Is RISC_CORE successfully linked?... Question 12. What designs are accessible (via current_design) in PT memory (HINT: get_designs *)? Reading design into PrimeTime

7 Task 2. Read the Top-level Design. Link using DB Sub Blocks 1. Using the provided alias (in.synopsys_pt.setup), remove all the designs and library in memory. pt_shell> alias clean pt_shell> clean NOTE: If you quit PT and start again, begin with source task1_solution.pt 2. Read the top-level design netlist of RISC_CORE as done in Task 1. pt_shell> read_verilog RISC_CORE.v Question 13. How would you link the top-level RISC_CORE design using the DB sub blocks contained in the./source/db directory? Link RISC_CORE using DB sub blocks. pt_shell> lappend search_path./source/db pt_shell> link Question 14. Is the design successfully linked?... Question 15. Are there any unresolved references? Take a look at the./source/db directory. The ALU sub design has been mistakenly (or intentionally) written out as alu.db instead of ALU.db. PT looks for DESIGN.db file (case sensitive) to be able to resolve a DESIGN reference. Fix the problem and relink. pt_shell> ls al./source/db pt_shell> read_db alu.db pt_shell> link Reading design into PrimeTime 3-7

8 Question 16. What is one other way by which you could have resolved ALU?... Question 17. What design has been successfully linked? Here again, you accidentally linked a sub design (ALU) instead of RISC_CORE. The following command will fix this error. pt_shell> current_design RISC_CORE pt_shell> link Question 18. Is RISC_CORE successfully linked?... Question 19. What designs are accessible (via current_design) in PT memory (HINT: get_designs *)? You can free some memory and improve performance by removing the sub designs after successfully linking. Note: You can only perform STA at the RISC_CORE level. You cannot access the sub designs any more. pt_shell> current_design RISC_CORE pt_shell> link remove_sub_designs Question 20. Is RISC_CORE successfully linked?... Question 21. What designs are accessible (via current_design) in PT memory (HINT: get_designs *)?... Task 3. Read and Link a Top-level Hierarchical Design; Access Design Objects The objective of this task is to efficiently read and link a single DB file containing the Top and ALL the sub blocks. Question 22. What does a DB file contain (as compared to a Verilog or VHDL netlist)?... NOTE: If you quit PT and start again, begin with source task2_solution.pt 3-8 Reading design into PrimeTime

9 1. Remove any designs and the library from PT memory. Read ONLY the netlist out of the RISC_CORE hierarchical DB file. pt_shell> clean pt_shell> read_db netlist_only RISC_CORE_hier.db Question 23. What designs are accessible in PT memory (HINT: get_designs *)?... Question 24. How many designs are accessible in PT memory (HINT: sizeof_collection [get_designs *])?... Question 25. What is the current_design? Link the design to remove sub designs. pt_shell> link_design remove_sub_designs Question 26. What designs are accessible in PT memory (HINT: get_designs *)? Eventhough, the sub designs do not show up in the memory with the get_designs * command, you can still access hierarchically several objects in the design. Start by defining an alias to count the number of objects within a collection. pt_shell> alias size sizeof_collection Reading design into PrimeTime 3-9

10 4. Obtain the number of different objects in the current design and transfer them to Table 3-1 provided below: pt_shell> size [get_ports *] pt_shell> size [all_inputs] pt_shell> size [all_outputs] pt_shell> size [get_nets *] pt_shell> size [get_nets hier *] pt_shell> size [get_cells *] pt_shell> size [get_cells hier *] pt_shell> size [all_registers] pt_shell> size [get_pins *] pt_shell> size [get_pins -hier *] 5. Quit PrimeTime Object Type Number of Objects Ports # Total: # Inputs: Nets # Outputs # Top-level : Cells # In Entire hierarchy: # Top-level : # In Entire hierarchy: Pins # Registers # Top-level : # In Entire hierarchy: Table 3-1: Number of Objects in RISC_CORE pt_shell> quit Great! Now you are ready to answer a few challenging questions and compare your answers with the Solutions at the end of this Lab Reading design into PrimeTime

11 Task 4. Lab Review Questions Question 27. State 3 commands which make use of the search_path variable implicitly?... Question 28. What variable(s) is(are) used by the link command?... Question 29. How would you link sub blocks that are Verilog/VHDL netlist files?... Question 30. How would you link sub blocks that are DB netlists?... Question 31. How would you free up memory when using the link command on a large hierarchical design?... Question 32. When reading a design netlist file, which format (Verilog/VHDL/DB) benefits from the -netlist_only option?... Question 33. List at least 3 techiques that you learned by doing this lab: Reading design into PrimeTime 3-11

12 Answers for Task 1. Read the Top-level Design. Link using Verilog Sub Blocks Q 1. What was the problem? PT cannot read (find) the file. Q 2. What are the 2 ways you can fix this problem? Provide full path name of the design file (OR) update the search_path Q 3. Are there unresolved references? Yes Q 4. Is the design reported successfully linked? Yes Q 5. How many references are unresolved? 68 Q 6. Is the design reported successfully linked? No Q 7. How many references are unresolved? 7 Q 8. Are these library cells or sub blocks unresolved? sub blocks Q 9. Are there any unresolved references? No 3-12 Reading design into PrimeTime

13 Q 10. What design has been successfully linked now? Yes Q 11. Is RISC_CORE successfully linked? Yes Q 12. What designs are accessible (via current_design) in PT memory (HINT: get_designs *)? RISC_CORE and all its sub designs Task 2. Read the Top-level Design. Link using DB Sub Blocks Q 13. How would you link the top-level RISC_CORE design using the DB sub blocks contained in the./source/db directory? Update the search_path Q 14. Is the design linked successfully? No Q 15. Are there any unresolved references, which one? Yes, ALU Q 16. What is one other way by which you could have resolved ALU? unix% mv alu.db ALU.db pt_shell> current_design RISC_CORE pt_shell> link Q 17. What design has been linked successfully? ALU Q 18. Is RISC_CORE linked successfully? Yes Reading design into PrimeTime 3-13

14 Q 19. What designs are accessible (via current_design) in PT memory (HINT: get_designs *)? RISC_CORE and all its sub designs Q 20. Is RISC_CORE successfully linked? Yes Q 21. What designs are accessible (via current_design) in PT memory (HINT: get_designs *)? RISC_CORE Task 3. Read and Link Top-level Hierarchical Netlist; Access Design Objects Q 22. What does a DB file contain (as compared to a Verilog or VHDL netlist)? DB file contains Gate level netlist and Constraints and attributes placed on the design Q 23. What designs are accessible in PT memory (HINT: get_designs *)? RISC_CORE, CONTROL, PRGRM_CNT_TOP, INSTRN_LAT, ALU, DATA_PATH, STACK_TOP, REG_FILE Q 24. How many designs are accessible in PT memory (HINT: sizeof_collection [get_designs *])? 8 Q 25. What is the current_design? RISC_CORE Q 26. What designs are accessible in PT memory (HINT: get_designs *)? RISC_CORE 3-14 Reading design into PrimeTime

15 Object Type Number of Objects Ports # Total: 98 # Inputs: 35 # Outputs 63 Nets # Top-level : 299 # In Entire hierarchy: 2859 Cells # Top-level : 68 # In Entire hierarchy: 2259 # Registers 301 Pins # Top-level : 618 # In Entire hierarchy: 8800 Table 3-1: Number of Objects in RISC_CORE Task 4. Lab Review Questions Q 27. State 3 commands which make use of the search_path variable implicitly? read_verilog, read_db, link_design, source Q 28. What variable(s) is(are) used by the link command? link_path, search_path, link_create_black_boxes Q 29. How would you link sub blocks that are Verilog/VHDL netlist files? Read them in explicitely into PT memory using read_veriolog or read_vhdl Q 30. How would you link sub blocks that are DB netlists? Append the search_path for the directory with DB files. Then link Q 31. How would you free up memory when using the link command on a large hierarchical design? link remove_sub_designs option Q 32. When reading a design netlist file, which format (Verilog/VHDL/DB) benefits from the -netlist_only option? DB Reading design into PrimeTime 3-15

16 Q 33. List at least 3 techniques that you learned by doing this lab: 1) Before reading in a design netlist file, search_path should be updated to the directory containing the design file(s). 2) Before linking a design, make sure that link_path contains PT memory (*) and that the library DB file and the search_path contain the directories of the Library file, as well as any sub design files. 3) Use current_design command before linking a design. The End of Lab Reading design into PrimeTime

Agenda: Day One 3-1 DAY. Welcome. Introduction to Static Timing Analysis. Writing Basic Tcl Constructs in PT. Constraining Internal Reg-Reg paths

Agenda: Day One 3-1 DAY. Welcome. Introduction to Static Timing Analysis. Writing Basic Tcl Constructs in PT. Constraining Internal Reg-Reg paths Agenda: Day One 3-1 DAY 1 Unit Register Register Paths Lab 0i Welcome 1 Introduction Static Timing Analysis 2 Writing Basic Tcl Constructs in PT 3 4 Constraining Internal Reg-Reg paths 3-1 Unit 3: Unit