Design Once with Design Compiler FPGA

Transcription

1 Design Once with Design Compiler FPGA The Best Solution for ASIC Prototyping Synopsys Inc.

2 Agenda Prototyping Challenges Design Compiler FPGA Overview Flexibility in Design Using DC FPGA and Altera Devices 2002 Synopsys, Inc. (2) CONFIDENTIAL

3 41% of our ASIC customers are prototyping their ASIC designs in FPGA Synopsys 2004 Implementation Seminar Survey ASIC Prototyping Not Using FPGA 41% 52% Full Production 5% 8% Pre-Production Customer s use of FPGA s Multiple Responses Allowed 2002 Synopsys, Inc. (3) CONFIDENTIAL

4 Compelling Needs are Fueling Prototyping Market Earlier integration ASIC Design Data FPGA Synthesis Earlier software development RTL Faster verification FPGA Prototyping Platform Avoid costly ASIC re-spins 2002 Synopsys, Inc. (4) CONFIDENTIAL

5 ASIC Prototyping Poses Complexity Challenges FPGAs are approaching ASIC-like complexity Require ASIC-strength solution ASIC Gates 10M 1M 100K 10K 1K Median ASIC Size Largest FPGA Available Timing Quality of Results is critical Many prototypes (such as, wireless) need to run at top speed Real World Interfaces do not slow down for prototypes 2002 Synopsys, Inc. (5) CONFIDENTIAL Cisco Wireless Card

6 Two Flows = Two Implementations Traditional Prototyping Flow Time-consuming manual process Design Compiler ASIC Flow RTL Constraints and Scripts RTL Modification Rewrite RTL Constraints and Scripts Different source, tools, IP and flows Manual Clock Gating FPGA IP Build to Verify Manual Post Processing RTL Modifications In Lab Debug Clock Gating DesignWare / ASIC IP Formality Time consuming, error prone, manual modifications Is design integrity guaranteed? Are they functionally equivalent? 2002 Synopsys, Inc. (6) CONFIDENTIAL

7 Agenda Prototyping Challenges Design Compiler FPGA Overview Flexibility in Design Using DC FPGA and Altera Devices 2002 Synopsys, Inc. (7) CONFIDENTIAL

8 Design Compiler FPGA Evolutionary Revolutionary Design Compiler FPGA Optimized + Adaptive Optimization Technology Industry standard ASIC-strength solution Best timing Fastest path to prototype 2002 Synopsys, Inc. (8) CONFIDENTIAL

9 Industry Standard ASIC-Strength Solution Built on Design Compiler Technology ASIC Reliability Proven through over 125,000 ASIC tapeouts Advanced Algorithms that deal with the most challenging designs Controllability Ability to customize the synthesis process to meet your design goals Formal verification support ASIC strength platforms 2002 Synopsys, Inc. (9) CONFIDENTIAL

10 Drawback of Traditional Inflexible Synthesis Process 100 Runtime Frequency (MHz) a b c d e f g h Traditional Synthesis Process Inflexible a b c d e f g h 2002 Synopsys, Inc. (10) CONFIDENTIAL

11 Adaptive Optimization Technology Delivers the Best Timing Frequency ( (Mhz Mhz) Traditional Synthesis Process Inflexible a b c Runtime d a b c d e f g h e f g h Select best synthesis algorithms 2002 Synopsys, Inc. (11) CONFIDENTIAL

12 Adaptive Optimization Technology Delivers the Best Timing Frequency (MHz) Traditional Synthesis Process Inflexible a b c Runtime D d a b c d e f g h D e f G g H h G H Select best synthesis algorithms Dynamically tune algorithms 2002 Synopsys, Inc. (12) CONFIDENTIAL

13 Adaptive Optimization Technology Delivers the Best Timing Frequency (MHz) Traditional Synthesis Process Inflexible Adaptive Optimization Technology G a D b c Runtime H d a b c d e f g h G D H e f g h Frequency Traditional ~15% Better AOT Select best synthesis algorithms Dynamically tune algorithms Re-order algorithms 2002 Synopsys, Inc. (13) CONFIDENTIAL

14 Design Once With Design Compiler FPGA Traditional Prototyping Flow ASIC Flow Design Compiler ASIC-Strength Prototyping Flow Design Compiler FPGA RTL RTL Modification RTL RTL Constraints and Scripts Rewrite Constraints and Scripts Constraints and Scripts Manual Clock Gating Manual Post Processing Clock Gating Automatic Clock Gating Transformation FPGA IP RTL Modifications DesignWare / ASIC IP DesignWare / ASIC IP Build to Verify In Lab Debug Formality Formality Likely Errors Design Integrity Ensured 2002 Synopsys, Inc. (14) CONFIDENTIAL

15 ASIC-Strength Flow at Alereon The [DC FPGA] methodology and flow were exactly the same as Design Compiler so we were able to use the same scripts, constraints and RTL from the ASIC design. - Dave Ohmann, IC Design Engineer 2002 Synopsys, Inc. (15) CONFIDENTIAL

16 Best Timing at AMD A significant speed increase over what we were able to achieve with other FPGA synthesis tools. - Dirk Haentzschel, Sr. Design Engineer 2002 Synopsys, Inc. (16) CONFIDENTIAL

17 Fastest Path to Prototype at Matrix Semiconductor Design Compiler FPGA was the only FPGA synthesis solution that had an integrated ASIC/FPGA flow, providing the easiest path to prototype our technology. -James Tringali, ASIC Design Manager 2002 Synopsys, Inc. (17) CONFIDENTIAL

18 Agenda Prototyping Challenges Design Compiler FPGA Overview Flexibility in Design Using DC FPGA and Altera Devices 2002 Synopsys, Inc. (18) CONFIDENTIAL

19 Design Once Implementation Flow RTL, Constraints Synthesis Design Compiler FPGA Design Compiler Prototyping Platform Production Altera FPGA Altera HardCopy ASIC Time Time Time 2002 Synopsys, Inc. (19) CONFIDENTIAL

20 ASIC Strength Flow for Flexibility RTL, Constraints PrimeTime Synthesis Fitter Design Compiler FPGA Quartus II Static Timing Timing Analysis Analysis Gate-Level Simulation Programming Formal Verification Post-P&R Verification Power Estimation In-System Debug VCS Formality 2002 Synopsys, Inc. (20) CONFIDENTIAL

21 Design Compiler FPGA Supported Devices and Platforms Stratix TM Stratix TM GX HardCopy TM Stratix TM II (Available ) Cyclone TM Cyclone TM II (Available ) DC FPGA is available today on: Solaris (32 and 64 bit) and Linux 2002 Synopsys, Inc. (21) CONFIDENTIAL

22 DC FPGA is Having Significant Success Over 80 Customers 2002 Synopsys, Inc. (22) CONFIDENTIAL

23 Fastest Path to Prototype DC FPGA Partners Automated Partitioning DSP Algorithms in Silicon Embedded Instrumentation Hardware Assisted Verification Configurable Cores Reconfigurable Prototyping Platforms 2002 Synopsys, Inc. (23) CONFIDENTIAL

24 Summary Design Compiler FPGA Industry standard ASIC-strength solution Flexibility and Stability of DC Advanced Algorithms Best timing Adaptive Optimization TM Technology Fastest path to prototype Ensuring Design Integrity between Prototype and ASIC Flexibility to target Altera FPGA or HardCopy Devices Design Once! 2002 Synopsys, Inc. (24) CONFIDENTIAL