Ai2410. A1 PROs. Block Diagram. Signal Processor for Single-Chip CCD B/W Camera. 64 pin LQFP (7x7) VEE
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1 A1 PROs Signal Processor for Single-Chip CCD B/W Camera Description The is a signal processor for CCD B/W camera application. It combines CCD analog signal processor, timing logic controller and vertical into one single chip. 64 pin LQFP (7x7) Function Timing Logic Controller CDS (Correlated Double Sampling) o AGC (Automatic Gain Control) Absolute Maximum Ratings (Ta = 25 C ) Gamma Corrections Parameter Rating Unit ideo Driver ertical Driver Supply voltage cc, DD 7 Supply voltage Reference Features 5 steps sample and hold Wide dynamic range -4 to 32dB of AGC Built-in Opamp for AGC control loop 3 Mode dark-clip control 2 Mode white-clip control 75 ohm video driver and SAG compensation Auto Iris and electronic shutter mode Supports EIA/ CCIR of 510H/760H system CCD image sensors 760H: MHz (EIA) and MHz (CCIR) 510H: MHz (EIA), MHz (CCIR) Built-in sync signal generation function Support external sync function EE Supply voltage HH, Storage Temperature Operating Temperature ME STG EE HH voltage to T 65 ~ OPR Allowable Power Dissipation P D Operating Conditions T 20 ~ + 75 o C o C 500 mw Parameter Rating Unit Supply oltage cc, DD 4.75 ~ 5.25 Supply voltage Supply voltage HH ME EE EE Application CCD monochrome camera Structure BiCMOS silicon monolithic IC Block Diagram
2 CCD Signal Processor Timing Logic Controller 2
3 ertical Driver 3
4 PIN Configuration 4
5 Pin Description Timing Logic Controller No Symbol I/O Description. 3 RG O Reset gate pulse output 6 CLP1O O Pulse output for clamp 7 CLP2O O Pulse output for clamp 8 HD O Horizontal drive output 9 D O ertical drive output 10 CDD Digital power supply 11 SPUP I Shutter speed up reference voltage/ shutter speed setting; strobe input in serial mode 12 IRIN/ED1 I Iris signal input/shutter speed setting; clock input in serial mode 13 SPDN I Shutter speed down reference voltage/ shutter speed setting; data input in serial mode 14 reg I Bias current supply for comparator 15 CGND Digital ground 41 EXT O External sync/internal sync identification signal High: external sync; Low: internal sync 42 HBAND I Selection pin for normal (510H) / high band (760H) support 43 Mode5 I Low: Normal mode; High: Test mode (with pull-down resistance) 44 GND Digital ground 45 CKI I Clock Input 46 OSCOUT O Oscillation (crystal oscillator) inverter output 47 OSCIN I Oscillation (crystal oscillator) inverter input 48 DD Power supply 49 IRENB I Low: Electronic Shutter mode; High: Auto iris mode (with pull-up resistance) 50 ENB I XSUB pulse ON/OFF control (with pull-up resistance) Low: XSUB pulse output stop; High: XSUB pulse output 51 Mode2 I Electronic shutter speed input switchover (with pull-up resistance) Low: serial input; High: parallel input 52 Mode1 I Low: EIA; High: CCIR (with pull-down resistance) 53 HCOMP O Comparator output (H phase comparator) 54 HPLL I Horizontal drive signal input (with pull-up resistance) 55 R/SYN I ertical drive signal input/composite sync input (with pull-up resistance) 56 ESYNC I Low: SYNC sync or internal sync; High: D/HD sync (with pull-down resistance) 5
6 CCD Signal Processor No Symbol I/O Specification Equivalent Circuit Description 16 CLP1 I Clamping input pin (active high) 17 Linear O Linear signal output pin cc :in 8 output signal turn to γ 2 output 18 γ OUT O Gamma compensation signal output pin γ 1 output when Pin 39 at open γ output when Pin 39 at DET OUT O Output pin of AGC detection signal 20 γ IN I Input pin of the gamma compensation circuit 6
7 21 γ CLP Capacitor connecting pin for gamma input clamp 22 AGC OUT O Output pin of signal passed through AGC 23 AGC MAX I DC Maximum gain setting pin of AGC amplifier 24 OP OUT O Output pin of operational amplifier 25 OP IN+ I Non-inverted input pin of the operational amplifier (AGC detection signal input pin) 26 OP IN- I Inverted input pin of the operational amplifier 7
8 27 AGC CONT I DC Gain control pin of AGC amplifier 28 DATA I CCD signal input pin 29 PG I CCD signal input pin 30 CLP2 I Clamping input pin (active high) 32 WCCONT I Input oltage GND White clip level adjusting pin Preset mode Control mode 34 DCCONT I Input oltage Dark clip level adjusting pin GND Preset mode Control mode cc Preset mode 2 8
9 35 IRIS CLP Capacitor connecting pin for IRIS output clamp 36 IRIS O Output pin of the IRIS control signal 37 SAG I Input pin of SAG compensation signal. AC couple from output Pin28 ideo through external capacitor 38 ideo O IDEO signal output pin 39 AGND Analog ground of CCD signal processor 40 ACC Analog supply of CCD signal processor 42 HBand/FLD O Digital Output 0-5 Field identification signal output (High: odd field; Low: even field) 31 REF_3-3 reference voltage Normally leave it open or supply 3 externally. 9
10 ertical Driver No Symbol I/O Description 1 H1 O H1 clock output for CCD horizontal register drive 2 H2 O H2 clock output for CCD horizontal register drive 4 HDD Power supply for H1 and H2 5 HGND GND for H1 and H2 57 HH Power supply (+15) 58 SUB O Output control (SUB) 59 2 O Output control ( φ 2 ) 60 1 O Output control ( φ1 ) 61 ME Power supply (0) 62 3 O 63 4 O Output control ( φ 3 ) Output control ( φ 4 ) 64 EE Power supply (-8.5) 10
11 Electrical Characteristics ( =5, T =25 o C ) DC Characteristic cc a Timing Logic Controller PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply oltage DD Input oltage IH 0.7 DD 0.3 DD IL Output voltage 1: OH1 I OH =-2mA DD -0.8 All output pins except OL1 I OL =4mA 0.4 those below) Output voltage 2: OH 2 I OH =-8mA DD -0.8 Pin 6 (RG) and Pin 8 OL2 I OL =8mA 0.4 (HCOMP) Output voltage 3: OH 3 I OH =-12mA DD -0.8 Pin 62 (H2) and Pin 63 OL3 I OL =12mA 0.4 (H1) Output voltage 4: OH 4 I OH =-1mA DD /2 Pin 3 (OSCOUT) OL4 I OL =1mA 0.4 Feedback resistance RFB IN =GND or DD 250k 1M 2.5M Ω Pull-up current Pull-down current I PU I PD IH I IL =0-80 μ A = 40 μ A DD Current consumption DD =5 Normal operating state AC Characteristic DD 28 ma SYMBOL Condition Min. Max. ts2 SPDN (ED2) setup time for IRIN (ED1) rise 20ns - th2 SPDN (ED2) hold time for IRIN (ED1) rise 20ns - 11
12 ts1 IRIN (ED1) setup time for SPUP (ED0) rise 20ns - tw0 SPUP (ED0) pulse width 20ns ts0 SPUP (ED0) setup time for IRIN (ED1) rise 20ns - CCD Signal Processor 50 μ s PARAMETER CONDITIONS MIN TYP MAX UNITS AGC Gain AGC dynamic range db AGC MAX = 4, AGC CONT = 1.5 and DATA IN = 100m db AGC CONT = 5 and DATA IN = 500m -4-1 db AGC CONT = 1.5 and DATA IN = 30m db AGC CONT = 3.55 and DATA IN = 320m db AGC OUT DC output level of AGC OUT γ γ IN=500m m 2 γ γ IN=500m m Linear Gain Gain between γ IN and Linear db γ IN =500m DET OUT DC output level of DET OUT IRIS DC output level of IRIS ideo Driver Gain between DATA Input and IRIS: DATA input = 300m db Gain between DRIE IN and IDEO: DRIE IN = 700m db SYNC Level m Dark Clip Preset mode m White Clip Opamp Preset mode m DC CONT = m DC CONT = m DRIER IN = 1500m WC CONT = GND m WC CONT = m WC CONT = m DC output level of OP OUT OP IN+ = 2.5 and OP IN- = OP IN+ = 4 and OP IN- =
13 DC Characteristic ertical Driver Description Symbol Condition Min. Typ. Max. Unit Supply oltage Operation Current P SS I Shutter speed: 1/100000s ma P1 I Shutter speed: 1/100000s ma P0 I Shutter speed: 1/100000s ma SS Output Current I 1-4 = ma OL I 1-4 = ma OM 1 I 1,3= ma OM 2 I 1,3 = ma OH I SUB = ma OSL I SUB = ma OSH AC Characteristic ( = 15, =GND, =-8.5 and T =25 o C P1 P0 SS a Description Symbol Condition Min. Typ. Max. Unit Delay Time Rising Time TPLM No Load ns T No Load ns PMH T No Load ns PLH T No Load ns PML T No Load ns PHM T No Load ns PHL T ns PLM SS P0 T ns PMH P0 P1 T ns PLH SS P1 T ns PML P 0 SS T ns PHM P1 P0 T ns PHL CLH CLL P1 P0 Output Noise, 0.5 CMH, CML 13
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15 External Synchronization 1. External/Internal Sync Selection External or internal synchronization is selected automatically by a combination of 3 pins (R/SYNC, HPLL and ESYNC) to which the sync signal is input externally. The table below shows the input pattern combinations. Input R/SYNC pin: SYNC signal R/SYNC pin: D signal R/SYNC pin: SYNC signal pattern HPLL pin : Open HPLL pin : HD signal HPLL pin : Open ESYNC pin : Open ESYNC pin : DD ESYNC pin : Open EXT pin High High Low Output Sync state External sync External sync Internal sync Note ) Operation is possible even if the D cycle of the D input in the D/HD sync mode is longer than normal. The EXT pin is the external/internal sync identification signal output pin. This output signal can be used as the signal to select LC oscillation for expanding the lock range for external synchronization or the oscillator for improving the oscillation accuracy for internal synchronization. 2. Reset Operation SYNC synchronization The R1 signal component is extracted from the SYNC signal supplied externally and, for EIA, reset is performed so that the D pulse falls at the count of 259H ( H) from the fall of the R1 pulse. For CCIR, it is reset in such a way that the D pulse falls at the count of 309H( H).For these reasons, it is a prerequisite that the SYNC signal input comply with the EIA or CCIR standard. D/HD synchronization reset is performed so that the D pulse 1H later after detecting the fall of the D(DR) pulse supplied externally. Therefore, this enables reset operation regardless of the field line number. The phase difference between the DRpulse and HD pulse which is locked horizontally at PLL circuit identifies whether the field is odd or even. (DR must have a pulse width of 2H or more.) 15
16 Electronic Shutter/Auto IRIS By setting the ENB(Pin 7) high, the XSUB pulse is output for a specific period to activate the electronic shutter and auto iris. 1. Auto Iris (IRENB=high, MODE2=any level) No Symbol Function 25 IRIN/ED1 Iris signal input 23 SPDN/ED2 Shutter speed down reference voltage 24 SPUP/ED0 Shutter speed up reference voltage 2. Parallel input electronic shutter (IRENB=low, MODE2=high) No Symbol Function 23 SPDN/ED2 H H H H L L L L 25 IRIN/ED1 H H L L H H L L 24 SPUP/ED0 H L H L H L H L Shutter speed EIA: 1/100 1/250 1/500 1/1000 1/2000 1/5000 1/ / CCIR: 1/ Serial input electronic shutter (IRENB=low, MODE2=high) The ED2 data is latched in the register at the ED1 rise, and retrieved internally at the ED0 rise. Typical shutter speed EIA CCIR Load value Shutter speed Load value Shutter speed 00h 1/ h 1/ Eh 1/ Ah 1/ Ah 1/ h 1/ h 1/ h 1/2000 9Ch 1/ h 1/1000 ACh 1/500 A7h 1/500 CAh 1/250 C5h 1/250 EDh 1/100 E1h 1/120 16
17 Mode Control No. Symbol I/O Low High Remarks 7 ENB I XSUB stop XSUB output 20 IRENB I Electronic shutter Auto iris alid only when ENB is high 16 MODE2 I Serial input Parallel input alid only when ENB is high and IRENB is low 25 IRIN/ED1 I Auto iris control signal input pin (IRENB = high) alid only when ENB is high 23 SPDN/ED2 I Shutter speed setting pin (IRENB = low) 24 SPUP/ED0 I 15 MODE1 I EIA CCIR 11 HPLL I Internal sync: HPLL (open) R/SYNC (open) SYNC sync: HPLL (open) 10 R/SYNC I R/SYNC (SYNC input) D/HD sync: HPLL (HD input) R/SYNC (D input) 9 ESYNC I SYNC sync D/HD sync Internal sync 12 EXT O Internal sync External sync Switchover between internal and external sync is automatically identified by input state at Pin 9, 10 and 11 Mode Tables 1. Internal sync mode Interlace Field readout Frame readout XSUB pulse OFF 1 O O Electronic shutter ON O O Auto iris ON O O 1 EIA for 1/60 s accumulation; CCIR for 1/50 s accumulation O: Can be used 2. SYNC sync (external sync) mode Interlace Field readout Frame readout XSUB pulse OFF 1 O O Electronic shutter ON O O Auto iris ON O O 17
18 1 EIA for 1/60 s accumulation; CCIR for 1/50 s accumulation O: Can be used 3. D/HC sync (external sync) mode D input with normal cycle D input with longer cycle than Interlace normal interlace Field readout Frame readout Field readout Frame readout XSUB pulse OFF 1 O O O X Serial input electronic O O X X shutter ON Parallel input electronic shutter ON O O X X Auto iris ON O O X X 1 EIA for 1/60 s accumulation; CCIR for 1/50 s accumulation O: Can be used X: Cannot be used Note Only in the D/HD sync mode, the external synchronization is possible during which D pulses with longer cycle than normal are input to the R/SYNC pin 18
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27 REISION HISTORY Revision Description Date 1.0 Release 9 May
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